Automating the design of SOCs using cores

Bergamaschi, Reinaldo A.; Bhattacharya, Subhrajit; Wagner, R.J.; Fellenz, C.; Muhlada, M.; White, F. R.; Daveau, Jean-Marc; Lee, W.R.

doi:10.1109/54.953270

Cited by 64 publications

(21 citation statements)

References 4 publications

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“…We first defined an input sequence for the simulation (1). From this sequence with which the first stage of the matrix multiplication pipeline is triggered, we computed the upper and lower arrival curves which are used for the formal analysis method (2). We then performed the simulation of the system and the analysis (3), and calculated the arrival curve from the simulation output (4) in order to be able to compare the two approaches (5).…”

Section: Comparison Of the Approachesmentioning

confidence: 99%

“…Such a system may consist of several IP cores and dedicated hardware, as the Cell processor announced recently by Sony, IBM and Toshiba [15]. To shorten the design times, predefined and verified cores are used for newly designed systems [2]. Using cores, the designers can concentrate on overall system design instead of working on the individual components.…”

Section: Introductionmentioning

confidence: 99%

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Combining Simulation and Formal Methods for System-Level Performance Analysis

Kiinzli

Poletti

Benini

et al. 2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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Section: Comparison Of the Approachesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Combining Simulation and Formal Methods for System-Level Performance Analysis

Kiinzli

Poletti

Benini

et al. 2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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show abstract

“…Under these conditions, designers are developing ICs that integrate complex heterogeneous functional elements into a single chip, known as a system on a chip (SoC). As described by Gupta [2] and Bergamaschi [3] , SoC design is based on intellectual property (IP) cores reuse. Gupta in [2] define core as a pre-designed, preverified hardware piece that can be used as a building block for large and complex applications on an IC.…”

Section: Introductionmentioning

confidence: 99%

Study of Network on Chip resources allocation for QoS Management

Helali¹,

Soudani²,

Bhar³

et al. 2006

J. of Computer Science

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Abstract:The increasing complexity of integrated circuits and application requirements drive the research of new on-chip interconnection architectures. A network on chip draws on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. The main goal pursued is to achieve superior bandwidth when compared to conventional onchip bus architectures. The complexity of Systems-on-Chip (SoC) is growing; meeting real-time requirements is becoming increasingly difficult. Predictability for computation, memory and communication components are needed to build up real-time SoC. To achieve guaranteed throughput and bounded delivery delay, buffers in network interfaces (NIs) must be dimensioned to hide round-trip latency and rate difference between computation and IPs communication.. It is crucial to shape these buffers according to the network requirements and to bring out the right specification before the design step to provide desired performances in the SoC. In this field this paper describes and presents a performance analyses of NoC shaped on mesh architecture. The goal of this work is to quantify buffering requirements in the NoC nodes by the analyze of some QoS metrics such as drop, compute latency, and throughput. This study presented in this paper is based on simulation approach of a mesh (4 x 4 ) NoC behavior under multimedia communication process with MPEG-4 (Moving Picture Experts Group) flows.

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“…Unfortunately, embedded memories are scarce resources for which processors' instruction and data cache memories as well as bus and network on chip FIFO based interfaces will compete. This competition is dominated by the absolute requirement of efficiency in performance, area and energy consumption [13] In this paper we address this multi-objective optimization problem [8] restricted to performance and area through the combination of an efficient design space exploration (DSE) technique coupled with direct execution on an FPGA board [12]. The direct execution removes the prohibitive simulation time associated with the evaluation of embedded multiprocessor systems.…”

Section: Introductionmentioning

confidence: 99%

System-Level Design Methodology with Direct Execution For Multiprocessors on SoPC

Mouhoub

Hammami

7th International Symposium on Quality Electronic Design (ISQED'06)

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Contrary to ASIC design where resources can be tuned with respect to the need of the designer, systems on programmable chip SoPC (FPGA) have to make best use of 'off the shelf devices', where main resources are fixed. In this regard, embedded memories are of tremendous value because of their low latency. These embedded memories are not only used for data and program storage but also for all sorts of memory usage e.g. FIFO used by IP interfaces for bus and network on chip connection. The problem addressed by this paper is the optimal sizing of queues in the framework of SoPC. Current SoC design tools are of little help to define the most adequate size for these FIFOs and the large design space coupled with excessive simulation times make it even more difficult. We propose in this paper an automatic tuning technique of queue sizes in IP interfaces for system on programmable chip with hardware in the loop execution. An application of our technique on Virtex-II SoPC is described.

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Automating the design of SOCs using cores

Cited by 64 publications

References 4 publications

Combining Simulation and Formal Methods for System-Level Performance Analysis

Combining Simulation and Formal Methods for System-Level Performance Analysis

Study of Network on Chip resources allocation for QoS Management

System-Level Design Methodology with Direct Execution For Multiprocessors on SoPC

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