Study of Network on Chip resources allocation for QoS Management

Abstract

Abstract:The increasing complexity of integrated circuits and application requirements drive the research of new on-chip interconnection architectures. A network on chip draws on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. The main goal pursued is to achieve superior bandwidth when compared to conventional onchip bus architectures. The complexity of Systems-on-Chip (SoC) is growing; meeting real-time requirements is becoming increasingly difficult. Predictability for computation, memory and communication components are needed to build up real-time SoC. To achieve guaranteed throughput and bounded delivery delay, buffers in network interfaces (NIs) must be dimensioned to hide round-trip latency and rate difference between computation and IPs communication.. It is crucial to shape these buffers according to the network requirements and to bring out the right specification before the design step to provide desired performances in the SoC. In this field this paper describes and presents a performance analyses of NoC shaped on mesh architecture. The goal of this work is to quantify buffering requirements in the NoC nodes by the analyze of some QoS metrics such as drop, compute latency, and throughput. This study presented in this paper is based on simulation approach of a mesh (4 x 4 ) NoC behavior under multimedia communication process with MPEG-4 (Moving Picture Experts Group) flows.

Exploring Optimal Topology and Routing Algorithm for 3D Network on Chip

“…Starting with 0.25 µm CMOS technology, wire delay dominates gate delay and the gap between wire delay and gate delay becomes wider as process technology improves, thus wires, not transistors are determining the performance of chips. Increase in number of transistors in a chip permits chip designers to integrate various components of an electronic system on a single IC to implement a complete System on a Chip (SoC) in which various components are named as cores or Intellectual Property (IP) blocks which include microprocessor, DSP, memory unit, I/O controller, analog signal or Radio Frequency module (Helali et al, 2006).…”

“…NoC is an on-chip communication methodology proposed to resolve the increased interconnection problems in SoC. In NoC paradigm, IP blocks are connected to a packet switched network through routers, in turn routers are interconnected each other to accomplish on chip communications (Helali et al, 2006;Dally and Towles, 2001). NoC applies packet switching network theories to on-chip communications.…”

End to End QoS Metrics Modeling Based on Multi-application Environment in Network on Chip

“…References [17], [18] and [19] addressed the problem of metrics for end-to-end QoS management on real-time applications by presenting a virtual communication support. Their research was focused on the study of QoS through the switch buffering requirements.…”

NOC: QOS Metrics Modelling And Analysis Based On Dynamic Routing

“…Helali and All addressed the problem of metrics for end-to-end QoS management on real time applications by presenting a virtual communication support [15]. Their research was focused on the study of QoS through the switch buffering requirements [16]. In [17] they were interested on NoC switch scheduling and its impact on QoS metrics.…”