Automatic testcase synthesis and performance model validation for highperformance PowerPC processors

Bell, Robert H.; Bhatia, R.; John, Lizy K.; Stuecheli, Jeffrey; Griswell, John; Tu, Peishan; Capps, L.; Blanchard, Allan; Thai, Ryan

doi:10.1109/ispass.2006.1620800

Cited by 4 publications

(6 citation statements)

References 19 publications

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“…The number of frameworks proposed since then has been growing continuously corroborating their importance for the community. In contrast to our adaptive framework, particular solutions -without the micro-architecture semantics of MicroProbewere developed for different purposes: to generate synthetic microbenchmarks [2][3][4]26], to be able to reproduce proprietary application behavior [30,32], to perform architecture explorations [31], to generate power or reliability stress tests [20,21,33,39], to evaluate energy efficiency of systems [13], or to model cache behavior [1].…”

Section: Related Workmentioning

confidence: 99%

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

Bertran

Buyuktosunoglu

Gupta

et al. 2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

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Microprocessor-based systems today are composed of multi-core, multi-threaded processors with complex cache hierarchies and gigabytes of main memory. Accurate characterization of such a system, through predictive pre-silicon modeling and/or diagnostic postsilicon measurement based analysis are increasingly cumbersome and error prone. This is especially true of energy-related characterization studies. In this paper, we take the position that automated micro-benchmarks generated with particular objectives in mind hold the key to obtaining accurate energy-related characterization. As such, we first present a flexible micro-benchmark generation framework (MicroProbe) that is used to probe complex multi-core/multithreaded systems with a variety and range of energy-related queries in mind. We then present experimental results centered around an IBM POWER7 CMP/SMT system to demonstrate how the systematically generated micro-benchmarks can be used to answer three specific queries: (a) How to project application-specific (and if needed, phase-specific) power consumption with component-wise breakdowns? (b) How to measure energy-per-instruction (EPI) values for the target machine? (c) How to bound the worst-case (maximum) power consumption in order to determine safe, but practical (i.e. affordable) packaging or cooling solutions? The solution approaches to the above problems are all new. Hardware measurement based analysis shows superior power projection accuracy (with error margins of less than 2.3% across SPEC CPU2006) as well as maxpower stressing capability (with 10.7% increase in processor power over the very worst-case power seen during the execution of SPEC CPU2006 applications).

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Section: Related Workmentioning

confidence: 99%

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

Bertran

Buyuktosunoglu

Gupta

et al. 2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

View full text Add to dashboard Cite

show abstract

“…Development is generally top-down, starting with analysis of overall instruction flow and finishing with detailed microarchitectural tradeoffs. In a development environment, a new hardware design is usually based on an old prior design, and, likewise, the associated old performance model is enlisted for the new modeling effort, but only after the old model has been validated against the old hardware using a functional model compiled from a hardware description language (HDL) or by executing on a physical machine if it is available [4].…”

Section: Introductionmentioning

confidence: 99%

“…Validation of a hand-written performance model using an HDL model or hardware is a laborious and error prone process [5,7,4]. On a large, custom microprocessor design, many manmonths may be expended validating elements of the performance model against the hardware.…”

Section: Introductionmentioning

confidence: 99%

“…Hand-coded microbenchmarks [5] or synthetic codes [14] may be used to quickly validate specific instruction sequences. Automatic benchmark synthesis improves the process by reducing the number of instructions to be executed while assuring the representativeness of the codes [3,4]. Hardware acceleration systems built from FPGA arrays or custom hardware may be used to speedup processor simulations [4].…”

Section: Introductionmentioning

confidence: 99%

“…Automatic benchmark synthesis improves the process by reducing the number of instructions to be executed while assuring the representativeness of the codes [3,4]. Hardware acceleration systems built from FPGA arrays or custom hardware may be used to speedup processor simulations [4]. Despite these techniques, HDL model simulation speeds may be orders of magnitude slower than native hardware execution [4].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Automatic performance model synthesis from hardware verification models

Bell

Cummings

Jackson

2011

Proceedings of the 2nd ACM/SPEC International Conference on Performance Engineering

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Performance models are typically written by hand for a new model or assembled piece-meal from the prior simulation code of an old model. In either case, many man-months of work may be required to write the new model and validate design details against a prior or current design. In reality, the majority of information about the performance of the design already exists in the design structure of either the old hardware model or the new model or both.To harvest this information and eliminate the significant duplicate coding and validation efforts, we propose that a performance model be automatically synthesized from a prior or current hardware design using a bottom-up, design-oriented approach. We demarcate the performance-critical boundaries of the design and perform backward-trace cone analysis to identify logic to include in the performance model. We then abstract specific components for design changes and expend modeling effort only on the few functions relevant to a particular design study. Engineering effort then becomes focused on workload selection and quality, defining and projecting new designs, and assessing design tradeoffs and sensitivities -the small set of tasks with the highest potential to improve design performance.We present a case-study that shows that even the simplest proposed transformations on a high-performance IBM L2 cache design result in a simulation speedup of 3.9, with evidence that an order of magnitude speedup can be obtained using a few additional modeling abstractions.

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Halo

Panda

John

2018

Proceedings of the 2018 International Conference on Supercomputing

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Automatic testcase synthesis and performance model validation for highperformance PowerPC processors

Cited by 4 publications

References 19 publications

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

Automatic performance model synthesis from hardware verification models

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