Several factors describe the broad pattern of diversity in plant species distribution. We explore these determinants of species richness in Western Himalayas using high‐resolution species data available for the area to energy, water, physiography and anthropogenic disturbance. The floral data involves 1279 species from 1178 spatial locations and 738 sample plots of a national database. We evaluated their correlation with 8‐environmental variables, selected on the basis of correlation coefficients and principal component loadings, using both linear (structural equation model) and nonlinear (generalised additive model) techniques. There were 645 genera and 176 families including 815 herbs, 213 shrubs, 190 trees, and 61 lianas. The nonlinear model explained the maximum deviance of 67.4% and showed the dominant contribution of climate on species richness with a 59% share. Energy variables (potential evapotranspiration and temperature seasonality) explained the deviance better than did water variables (aridity index and precipitation of the driest quarter). Temperature seasonality had the maximum impact on the species richness. The structural equation model confirmed the results of the nonlinear model but less efficiently. The mutual influences of the climatic variables were found to affect the predictions of the model significantly. To our knowledge, the 67.4% deviance found in the species richness pattern is one of the highest values reported in mountain studies. Broadly, climate described by water–energy dynamics provides the best explanation for the species richness pattern. Both modeling approaches supported the same conclusion that energy is the best predictor of species richness. The dry and cold conditions of the region account for the dominant contribution of energy on species richness.
For decades, the primary tools in alleviating the "Memory Wall" have been large cache hierarchies and data prefetchers. Both approaches, become more challenging in modern, Chip-multiprocessor (CMP) design. Increasing the last-level cache (LLC) size yields diminishing returns in terms of performance per Watt; given VLSI power scaling trends, this approach becomes hard to justify. These trends also impact hardware budgets for prefetchers. Moreover, in the context of CMPs running multiple concurrent processes, prefetching accuracy is critical to prevent cache pollution effects. These concerns point to the need for a light-weight prefetcher with high accuracy. Existing data prefetchers may generally be classified as low-overhead and low accuracy (Next-n, Stride, etc.) or high-overhead and high accuracy (STeMS, ISB). We propose B-Fetch: a data prefetcher driven by branch prediction and effective address value speculation. B-Fetch leverages control flow prediction to generate an expected future path of the executing application. It then speculatively computes the effective address of the load instructions along that path based upon a history of past register transformations. Detailed simulation using a cycle accurate simulator shows a geometric mean speedup of 23.4% for single-threaded workloads, improving to 28.6% for multi-application workloads over a baseline system without prefetching. We find that B-Fetch outperforms an existing "best-of-class" light-weight prefetcher under singlethreaded and multiprogrammed workloads by 9% on average, with 65% less storage overhead.
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