Automatic test knowledge extraction from VHDL (ATKET)

Vishakantaiah,; Abraham, Robin; Abadir,

doi:10.1109/dac.1992.227793

Cited by 55 publications

(10 citation statements)

References 6 publications

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“…This concept was generalized to fault path by Freeman [20]. A speedup of one to two orders of magnitude has been shown to be achievable through hierarchical testing over logic-level test generation [19]- [26].…”

Section: Introductionmentioning

confidence: 98%

Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits

Bhatia¹,

Jha

1998

IEEE Trans. VLSI Syst.

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This paper describes the first behavioral synthesis system that incorporates a hierarchical test generation approach to synthesize area-efficient and highly testable controller/data path circuits. Functional information of circuit modules is used during the synthesis process to facilitate complete and easy testability of the data path. The controller behavior is taken into account while targeting data path testability. No direct controllability of the controller outputs through scan or otherwise is assumed. The test set for the combined controller/data path is generated during synthesis in a very short time. Near 100% testability of combined controller and data path is achieved. The synthesis system easily handles large bit-width data path circuits with sequential loops and conditional branches in their behavioral specification, and scheduling constructs like multicycling, chaining and structural pipelining. An improvement of about three to four orders of magnitude was usually obtained in the test generation time for the synthesized benchmarks as compared to an efficient gate-level sequential test generator. The testability overheads are almost zero. Furthermore, in many cases at-speed testing is also possible.Index Terms-Controller/data path testing, hierarchical testability, high-level synthesis, synthesis for testability.

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Section: Introductionmentioning

confidence: 98%

Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits

Bhatia¹,

Jha

1998

IEEE Trans. VLSI Syst.

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“…Vishakantaiah et al introduced a tool called ATKET [14] for the extraction of test knowledge from behavioral descriptions. The tool exhibits the following characteristics -it uses behavioral specifications of modules in the circuit, considers both accessibility features of the modules as well as constraints on specific signals in the circuit, and generates test knowledge in a preprocessing stage.…”

Section: Knowledge Extraction From Behaviormentioning

confidence: 99%

“…The tool exhibits the following characteristics -it uses behavioral specifications of modules in the circuit, considers both accessibility features of the modules as well as constraints on specific signals in the circuit, and generates test knowledge in a preprocessing stage. The knowledge generated by ATKET in the form of test modes [14] can be used to facilitate synthesis for testability. Test knowledge for the example circuit EG-CKT shown in Figure 1 was automatically generated.…”

Section: Knowledge Extraction From Behaviormentioning

confidence: 99%

“…The behavioral specification of a module contains inherent knowledge that can be exploited to identify testability bottlenecks [14]. Once such bottlenecks have been identified, it is possible to eliminate some of them by modifying the original behavioral description with additional behavioral statements i.e., specify some additional behavior of the module to impart better testability.…”

Section: Introductionmentioning

confidence: 99%

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Generation of testable designs from behavioral descriptions using high level synthesis tools

Varma

Vishakantaiah

Abraham

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium

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This paper develops a synthesis-for-testability procedure wherein behavioral modeling techniques are used to generate testable designs. Knowledge about the accessibility of embedded modules is extracted from the behavioral design, analyzed, and any modification required subsequently incorporated in the behavioral design. Results show that when the resulting testable circuit is synthesized from this modified design using a high level synthesis tool, the overhead for testability is quite small, especially for large circuits.

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“…Lee and Pate1 [8] used an RTL description of data path circuits and a finite state machine description of controllers to generate test pattems for microprocessors. Vishakantaiah [22] used a test knowledge base to determine the fault propagation and justification paths. Recent effort in developing All of the existing research, though not directly related to behavioral model verification to uncover design errors, attempt to generate test pattems from a given behavioral model to replace the much more costly task of test pattem generation at the gate level.…”

Section: Testing Criteria For Vhdl Designsmentioning

confidence: 99%

On choosing test criteria for behavioral level hardware design verification

Mayhauser

Chen

Kok³

et al.

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)

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This paper proposes criteria for the verification of behavioral designs for hardware written in VHDL. The criteria are analogous to testing criteria for software, but were adapted to the specific needs and constructs of hardware designs written in VHDL. We examine the potential value of these criteria with respect to desirable properties for evaluation criteria that were originally developed for sofrware. Then we apply the VHDL criteria to several design examples with varying complexities to demonstrate their practical usefulness. Although, applying sofmare testing techniques to hardware design at the behavioral level is not new, this work, to the best of our knowledge, is the first attempt to analyze the approach from the theoretical point of view and to lay the groundwork for achieving error-free design at the behavioral level.

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Automatic test knowledge extraction from VHDL (ATKET)

Cited by 55 publications

References 6 publications

Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits

Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits

Generation of testable designs from behavioral descriptions using high level synthesis tools

On choosing test criteria for behavioral level hardware design verification

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