Generation of testable designs from behavioral descriptions using high level synthesis tools

Abstract

This paper develops a synthesis-for-testability procedure wherein behavioral modeling techniques are used to generate testable designs. Knowledge about the accessibility of embedded modules is extracted from the behavioral design, analyzed, and any modification required subsequently incorporated in the behavioral design. Results show that when the resulting testable circuit is synthesized from this modified design using a high level synthesis tool, the overhead for testability is quite small, especially for large circuits.

Ayse

“…An unconstrained scheduling problem tries to find the minimum (optimum) value for the execution latency (Wong, Potkonjak, & Dey, 2004) (i.e., the minimum number of clock cycles to perform all the operations in a given behavioral description). Note that the execution latency of the entire circuit is equal to the sum of the execution delays of the operations in the longest path from source vertex to sink vertex in a given DFG (Varma, Vishakantaiah, & Abraham, 1993). This longest path is called as critical path in the graph.…”