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Behavioral specification of a design can be used t o suggest behavioral modifications that improve testability ofthe design. Past work has been targeted at identifying the techniques that will enable such modifications. However, the impact of such behavioral modifications on the testability of a design has not been analyzed with regards to fault coverage and area overhead which is the focus of this paper. Results obtained show that the area overhead is low and the fault coverage is higher when the behavior is modified f o r testability. These results are compared with the results obtained when partial scan is used to improve the testability of a design.

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Testability is becoming an increasing concern in the design of present-day VLSI systems because of their higher density and complexity. This is particularly important in the case of arithmetic units, such as adders, which form the core of any processing unit. Techniques like Design For Testability (DFT) have been implemented, but a methodology for evaluating and selecting a suitable adder has not been developed. In this paper, we present an exhaustive comparison of adders in terms of performance, area and testability, by formulating a figure of merit, the PLUS factor. The results of this comparison can be extended to evaluate the suitability of an adder for a particular set of design goals and constraints.