Automatic Generation of Spatial and Temporal Memory Architectures for Embedded Video Processing Systems

Norell, Håkan; Lawal, Najeem; O’Nils, Mattias

doi:10.1155/2007/75368

Cited by 4 publications

(1 citation statement)

References 17 publications

(29 reference statements)

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“…At Present, FPGA chips consist of many cores which make it ideal candidate for designing VSNs. A design methodology for mapping computer vision algorithm onto an FPGA by using coarse grain reconfigurable data flow graph is discussed in Sen, Corretjer, Haim, Saha, Jason, Bhattacharyya, and Wolf (2007) and Norell, Lawal, and O'Nils (2007). The pros and cons of FPGA technology and its suitability for computer vision task are discussed in (MacLean, 2005).…”

Section: Related Workmentioning

confidence: 99%

Architecture Exploration Based on Tasks Partitioning Between Hardware, Software and Locality for a Wireless Vision Sensor Node

Imran

Khursheed

Malik

et al. 2012

International Journal of Distributed Systems and Technologies

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Wireless Vision Sensor Networks (WVSNs) is an emerging field which consists of a number of Visual Sensor Nodes (VSNs). Compared to traditional sensor networks, WVSNs operates on two dimensional data, which requires high bandwidth and high energy consumption. In order to minimize the energy consumption, the focus is on finding energy efficient and programmable architectures for the VSN by partitioning the vision tasks among hardware (FPGA), software (Micro-controller) and locality (sensor node or server). The energy consumption, cost and design time of different processing strategies is analyzed for the implementation of VSN. Moreover, the processing energy and communication energy consumption of VSN is investigated in order to maximize the lifetime. Results show that by introducing a reconfigurable platform such as FPGA with small static power consumption and by transmitting the compressed images after pixel based tasks from the VSN results in longer battery lifetime for the VSN.

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Section: Related Workmentioning

confidence: 99%

Architecture Exploration Based on Tasks Partitioning Between Hardware, Software and Locality for a Wireless Vision Sensor Node

Imran

Khursheed

Malik

et al. 2012

International Journal of Distributed Systems and Technologies

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Video Processing Real-Time Algorithm Design Verification on Embedded System for HDTV

Zlokolica

Uzelac

Miljković

et al. 2009

2009 First IEEE Eastern European Conference on the Engineering of Computer Based Systems

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Embedded systems are considered as favorable frame-work for real-time Consumer Electronics (CE) applications because of well balanced compromise between hardware resources and feature performance. In video processing applications, such as HDTV, the most critical part of data processing chain is real-time processing. In this paper, we address the real-time algorithm design verification for video processing in TV systems in Linux OS running on MIPS processors. Verification of such system is done using demanding applications currently present in the HDTV.

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Exploration of target architecture for a wireless camera based sensor node

et al. 2010

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Abstract. The challenges associated with wireless vision sensor networks are low energy consumption, less bandwidth and limited processing capabilities. In order to meet these challenges different approaches are proposed. Research in wireless vision sensor networks has been focused on two different assumptions, first is sending all data to the central base station without local processing, second approach is based on conducting all processing locally at the sensor node and transmitting only the final results. Our research is focused on partitioning the vision processing tasks between Senor node and central base station. In this paper we have added the exploration dimension to perform some of the vision tasks such as image capturing, background subtraction, segmentation and Tiff Group4 compression on FPGA while communication on microcontroller. The remaining vision processing tasks i.e. morphology, labeling, bubble remover and classification are processed on central base station. Our results show that the introduction of FPGA for some of the visual tasks will result in a longer life time for the visual sensor node while the architecture is still programmable. I. INTRODUCTIONTypically Vision Sensor Nodes (VSN) in Wireless Vision Sensor Networks (WVSN) consists of a camera for acquiring images, a processor for local image processing and a transceiver for communicating the results to the central base station. Due to the technological development in image sensors, sensor networking, distributed processing, low power processing and embedded systems smart camera networks can perform complex tasks using limited resources such as batteries, a wireless link and with a limited storage facility. Such camera based networks could easily be installed in out-doors areas where there is a limited availability of power, where access is difficult and it is inconvenient to modify the locations of the nodes or frequently change the batteries. VSN have been designed and implemented on microcontroller and microprocessor [1,4]. Often these solutions have high power consumption and moderate processing capabilities. Due to rapid development in the semiconductor technology, the single chip capacity of Field Programmable Gate Array (FPGA) increases greatly while its power consumption decreases tremendously [15]. Presently FPGA chips consist of many cores which makes it ideal candidate for the designing of VSN. As VSN needs to be capable of performing complex image processing such as image compression, which needs a lot of processing. High processing requirement is increased for an increased image size. Attention must be paid to the hardware/software co-design strategy to meet both processing and power requirements of VSN [8]. In [9] the authors designed a novel VSN based on a low cost, low power FPGA plus microcontroller System on Programmable Chip (SOPC). The authors in [10] have implemented a computer vision algorithm in hardware. They have provided a comparison of hardware and software implemented system using the same algorithm. It is c...

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Automatic Generation of Spatial and Temporal Memory Architectures for Embedded Video Processing Systems

Cited by 4 publications

References 17 publications

Architecture Exploration Based on Tasks Partitioning Between Hardware, Software and Locality for a Wireless Vision Sensor Node

Architecture Exploration Based on Tasks Partitioning Between Hardware, Software and Locality for a Wireless Vision Sensor Node

Video Processing Real-Time Algorithm Design Verification on Embedded System for HDTV

Exploration of target architecture for a wireless camera based sensor node

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