Exploration of target architecture for a wireless camera based sensor node

Abstract

Abstract. The challenges associated with wireless vision sensor networks are low energy consumption, less bandwidth and limited processing capabilities. In order to meet these challenges different approaches are proposed. Research in wireless vision sensor networks has been focused on two different assumptions, first is sending all data to the central base station without local processing, second approach is based on conducting all processing locally at the sensor node and transmitting only the final results. Our research is focused on partitioning the vision processing tasks between Senor node and central base station. In this paper we have added the exploration dimension to perform some of the vision tasks such as image capturing, background subtraction, segmentation and Tiff Group4 compression on FPGA while communication on microcontroller. The remaining vision processing tasks i.e. morphology, labeling, bubble remover and classification are processed on central base station. Our results show that the introduction of FPGA for some of the visual tasks will result in a longer life time for the visual sensor node while the architecture is still programmable. I. INTRODUCTIONTypically Vision Sensor Nodes (VSN) in Wireless Vision Sensor Networks (WVSN) consists of a camera for acquiring images, a processor for local image processing and a transceiver for communicating the results to the central base station. Due to the technological development in image sensors, sensor networking, distributed processing, low power processing and embedded systems smart camera networks can perform complex tasks using limited resources such as batteries, a wireless link and with a limited storage facility. Such camera based networks could easily be installed in out-doors areas where there is a limited availability of power, where access is difficult and it is inconvenient to modify the locations of the nodes or frequently change the batteries. VSN have been designed and implemented on microcontroller and microprocessor [1,4]. Often these solutions have high power consumption and moderate processing capabilities. Due to rapid development in the semiconductor technology, the single chip capacity of Field Programmable Gate Array (FPGA) increases greatly while its power consumption decreases tremendously [15]. Presently FPGA chips consist of many cores which makes it ideal candidate for the designing of VSN. As VSN needs to be capable of performing complex image processing such as image compression, which needs a lot of processing. High processing requirement is increased for an increased image size. Attention must be paid to the hardware/software co-design strategy to meet both processing and power requirements of VSN [8]. In [9] the authors designed a novel VSN based on a low cost, low power FPGA plus microcontroller System on Programmable Chip (SOPC). The authors in [10] have implemented a computer vision algorithm in hardware. They have provided a comparison of hardware and software implemented system using the same algorithm. It is c...

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