This paper presents an algorithm for the allocation of on-chip FPGA Block RAMs for the implementation of Real-Time Video Processing Systems. The effectiveness of the algorithm is shown through the implementation of realistic image processing systems. The algorithm, which is based on a heuristic, seeks the most cost-effective way of allocating memory objects to the FPGA Block RAMs. The experimental results obtained, show that this algorithm generates results which are close to the theoretical optimum for most design cases.
This paper presents a tool for automatic generation of the memory management implementation for spatial and temporal realtime video processing systems targeting field programmable gate arrays (FPGAs). The generator creates all the necessary memory and control functionality for a functional spatio-temporal video processing system. The required memory architecture is automatically optimized and mapped to the FPGAs' memory resources thus producing an efficient implementation in terms of used internal resources. The results in this paper show that the tool is able to efficiently and automatically generate all required memory management modules for both spatial and temporal real-time video processing systems.
Abstraci-Most operations invoked in video processing systems are neighborhood oriented. For a video system designer, this Limited spatio-temporal coUection of pixels represents a natural abstraction, In this paper, we present a basic set of ohject-oriented design entities. Entities, which can he combined to capture an interface and memory model at a conceptual level, with the neighborhood as an abstraction. These design entities, called IMEM, are implemented as an extension to SystemC. lMEM supports conceptual modeling that excludes implementation details and has explicit data dependency built-in to the model This makes IMEM a very efficient starting point for design-space exploration and system synthesis. We propose two workflows. The rust is a system development workflow, where IMEM represents the starting point of a gradual refinement process, supported by an automated design space exploration step. The second workflow, based on direct mapping of the interface and memory model is presented as being suitable for rapid prototyping. A spatio-temporal noise-reduction fdter is selected as a test-vehicle in order to demonstrate the feasihility of IMEM.
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