Automatic Design and Yield Enhancement of Data Converters

Abstract

Data converters play a key role in modern analog/mixed-signal systems. Accordingly, it is important to investigate their performance and yield under uncertain parameters over the design process. An efficient approach for automatic design and yield enhancement of data converters is presented. The proposed algorithm generates a general netlist for each data converter and improves transistor sizing to reach acceptable values for performance parameters with an evolutionary process, and finds the best yield simultaneously. The applied framework on two data converter structures demonstrates a reliable circuit with optimum performance, power consumption, and area overhead over a single evolutionary process in 0.18[Formula: see text][Formula: see text]m technology.

Yield‐aware sizing of pipeline ADC using a multiple‐objective evolutionary algorithm

“…Recently, the evolutionary automatic circuit design is one of the highest trending ideas because of the presenting of novel approaches in both analog and digital . The results show that evolutionary algorithms beyond the scope of conventional design can lead to more efficient and practical circuits and reveal impressive features .…”