Resilient design of current steering DACs using a transistor level approach

Mirzaie, Nahid; Shamsi, Hossein; Byun, Gyung-Su

doi:10.1007/s10470-016-0859-1

Cited by 11 publications

(8 citation statements)

References 24 publications

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“…Table lists some obtained structures with minimum power consumption. As it is declared that opamp scaling is not as effective as capacitor value in power consumption, this factor is not considered here .…”

Section: Experimental Implementation and Resultsmentioning

confidence: 99%

“…

e_{K T true/ C, i}^{2} = \frac{K T}{C_{f i} + n C_{s i}}

where C fi and C si are the i th stage feedback and sampling capacitors in order. The total input referred noise power for a k ‐stage pipeline ADC can be obtained as follows .

e_{K T true/ C, italictotal}^{2} = e_{K T true/ C, 1}^{2} + \frac{e_{K T / C, 2}^{2}}{G_{1}^{2}} + \frac{e_{K T / C, 3}^{2}}{G_{1}^{2} . G_{2}^{2}} + \dots prefix+ \frac{e_{K T / C, k}^{2}}{\prod_{i = 1}^{k - 1} {G_{i}}^{2}}

…”

Section: Experimental Implementation and Resultsmentioning

confidence: 99%

“…Table I lists some obtained structures with minimum power consumption. As it is declared that opamp scaling is not as effective as capacitor value in power consumption, this factor is not considered here [22,36]. Table I indicates that between the several representative bit patterns 2-2-2-2-2 structure with 0.96-pF sampling capacitor and 0.25 scaling factor has the minimum power consumption.…”

Section: Experimental Implementation and Resultsmentioning

confidence: 99%

“…where C fi and C si are the ith stage feedback and sampling capacitors in order. The total input referred noise power for a k-stage pipeline ADC can be obtained as follows [22].…”

Section: Experimental Implementation and Resultsmentioning

confidence: 99%

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Yield‐aware sizing of pipeline ADC using a multiple‐objective evolutionary algorithm

Mirzaie

Shamsi

Byun

2016

Circuit Theory & Apps

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Summary In this paper, an efficient and highly accurate algorithm for yield‐aware design of pipeline analog to digital converters (ADCs) based on a four‐step approach is presented. First, a general netlist is generated for the data converter building blocks. Then, using an evolutionary method, its best performance sizing is estimated. Finally, the yield gets enhanced to reach a desired value. With the same accuracy, the presented algorithm can achieve yield optimization by approximately five times less computational cost compared with a state‐of‐the‐art MC‐based method. The framework is applied to demonstrate a reliable converter with optimum performance, power consumption, speed and area overhead during a single running process. A prototype 10‐bit resolution, 10‐MS/s pipeline analog to digital converter has been simulated in a 0.18‐µm 1.8‐V CMOS process. Presented results, applying the proposed method, show important advantages in terms of accuracy and efficiency. Copyright © 2016 John Wiley & Sons, Ltd.

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Section: Experimental Implementation and Resultsmentioning

confidence: 99%

“…

e_{K T true/ C, i}^{2} = \frac{K T}{C_{f i} + n C_{s i}}

where C fi and C si are the i th stage feedback and sampling capacitors in order. The total input referred noise power for a k ‐stage pipeline ADC can be obtained as follows .

e_{K T true/ C, italictotal}^{2} = e_{K T true/ C, 1}^{2} + \frac{e_{K T / C, 2}^{2}}{G_{1}^{2}} + \frac{e_{K T / C, 3}^{2}}{G_{1}^{2} . G_{2}^{2}} + \dots prefix+ \frac{e_{K T / C, k}^{2}}{\prod_{i = 1}^{k - 1} {G_{i}}^{2}}

…”

Section: Experimental Implementation and Resultsmentioning

confidence: 99%

Section: Experimental Implementation and Resultsmentioning

confidence: 99%

“…where C fi and C si are the ith stage feedback and sampling capacitors in order. The total input referred noise power for a k-stage pipeline ADC can be obtained as follows [22].…”

Section: Experimental Implementation and Resultsmentioning

confidence: 99%

See 2 more Smart Citations

Yield‐aware sizing of pipeline ADC using a multiple‐objective evolutionary algorithm

Mirzaie

Shamsi

Byun

2016

Circuit Theory & Apps

Self Cite

View full text Add to dashboard Cite

show abstract

“…It was provided with a 3.3V power supply and observed 0.6 LSB OF INL. [15] proposed a design of steering DAC. It was provided with transistor level synthesis.…”

Section: Introductionmentioning

confidence: 99%

A 10-bit 150MS/s Pipelined ADC with 2.5bit Gain Stage for High Frequency Applications

2019

IJITEE

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This paper proposes a 10-bit pipelined Analog to Digital Converter (ADC) which incorporates various techniques for lesser power and higher performance. The proposed method reduces the computational burden while comparing to the modified Monte-Carlo (MC) method. Pipelined ADC has N number of stages, it has higher resolution and higher frequency of conversion while comparing to other ADCs. The proposed ADC employs five 2.5bit gain stages; instead of 1.5bit gain stages for high accuracy. This method is implemented in the Tanner Software with the Generic 250nm library at a maximum power supply of 5V. The maximum frequency attained is 150MHz; and the ADC exhibits a SNR of 61.96dB. It also attains a 10bits as effective number of bits at the maximum sampling rate.

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Design and Analysis of an Ultra-Low-Power Second-Order Asynchronous Delta–Sigma Modulator

Akbari

Hashemipour

Moradi

2017

Circuits Syst Signal Process

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Resilient design of current steering DACs using a transistor level approach

Cited by 11 publications

References 24 publications

Yield‐aware sizing of pipeline ADC using a multiple‐objective evolutionary algorithm

Yield‐aware sizing of pipeline ADC using a multiple‐objective evolutionary algorithm

A 10-bit 150MS/s Pipelined ADC with 2.5bit Gain Stage for High Frequency Applications

Design and Analysis of an Ultra-Low-Power Second-Order Asynchronous Delta–Sigma Modulator

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