Automatic decomposition for sequential equivalence checking of system level and RTL descriptions

Vasudevan, Shobha; Abraham, Jacob A.; Viswanath, Vinod; Tu, Jiajin

doi:10.1109/memcod.2006.1695903

Cited by 23 publications

(11 citation statements)

References 9 publications

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“…Theoretically speaking, if we have a trustworthy high-level model of the design, we can resort to formal verification (FV) techniques [23] to check its equivalence with the questionable design for HT detection. In practice, however, FV techniques are usually not scalable to large circuits and the trusted high-level model may not be available.…”

Section: Verification For Hardware Trustmentioning

confidence: 99%

VeriTrust: Verification for Hardware Trust

Zhang

Yuan

Wei

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

168

120

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Hardware Trojans (HTs) implemented by adversaries serve as backdoors to subvert or augment the normal operation of infected devices, which may lead to functionality changes, sensitive information leakages, or Denial of Service attacks. To tackle such threats, this paper proposes a novel verification technique for hardware trust, namely VeriTrust, which facilitates to detect HTs inserted at design stage. Based on the observation that HTs are usually activated by dedicated trigger inputs that are not sensitized with verification test cases, VeriTrust automatically identifies such potential HT trigger inputs by examining verification corners. The key difference between VeriTrust and existing HT detection techniques is that VeriTrust is insensitive to the implementation style of HTs. Experimental results show that VeriTrust is able to detect all HTs evaluated in this paper (constructed based on various HT design methodologies shown in the literature) at the cost of moderate extra verification time, which is not possible with existing solutions.

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Section: Verification For Hardware Trustmentioning

confidence: 99%

VeriTrust: Verification for Hardware Trust

Zhang

Yuan

Wei

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

168

120

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“…Examples of such tools include "ImpulseC" [9], "CatapultC" [10] and "Cameron" [11], which map C-like script applications to FPGAs, "Calypto" [12] and "Sequential Equivalence Checking Tool" [13], which map SystemC scripts into RTL implementations by checking sequential equivalence of a system level model and its RTL version. The most prominent is perhaps AccelDSP by Xilinx, which takes input description in MATLAB.…”

Section: High Level Synthesis Flowmentioning

confidence: 99%

An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization

Kim

Deng

Mangalagiri

et al. 2009

IEEE Trans. Comput.

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Abstract-This paper describes TANOR, an automated framework for designing hardware accelerators for numerical computation on reconfigurable platforms. Applications utilizing numerical algorithms on large-size data sets require high-throughput computation platforms. The focus is on N-body interaction problems which have a wide range of applications spanning from astrophysics to molecular dynamics. The TANOR design flow starts with a MATLAB description of a particular interaction function, its parameters, and certain architectural constraints specified through a graphical user interface. Subsequently, TANOR automatically generates a configuration bitstream for a target FPGA along with associated drivers and control software necessary to direct the application from a host PC. Architectural exploration is facilitated through support for fully custom fixed-point and floating point representations in addition to standard number representations such as single precision floating point. Moreover, TANOR enables joint exploration of algorithmic and architectural variations in realizing efficient hardware accelerators. TANOR's capabilities have been demonstrated for three different N-body interaction applications: the calculation of gravitational potential in astrophysics, the diffusion or convolution with Gaussian kernel common in image processing applications, and the force calculation with vector-valued kernel function in molecular dynamics simulation. Experimental results show that TANOR-generated hardware accelerators achieve lower resource utilization without compromising numerical accuracy, in comparison to other existing custom accelerators.

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“…RELATED WORK Several approaches have been proposed to verify systemlevel specifications versus HDL descriptions [1], [4], [5], [6]. Vasudevan et al apply equivalence checking [4] to verify system-level design descriptions against their implementations in RTL. However, a cycle-accurate behavior of both descriptions is assumed.…”

Section: Introductionmentioning

confidence: 99%

Debugging HDL designs based on functional equivalences with high-level specifications

Finder

Witte

Fey

2013

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Abstract-The increasing complexity of circuits and systems is forcing design specifications to software-like programming languages like C. Since the conversion from software to hardware is a difficult task solved manually, bugs are frequently introduced in the HDL design. Sophisticated automated error localization and correction techniques, i.e. debugging, are a challenge.In this paper a new automated method is presented for debugging hardware implementations when a software-like specification in C is given. Based on functional equivalences between software and hardware, error localization and correction are automated. We present experimental results for different types of designs and different types of faults.

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Automatic decomposition for sequential equivalence checking of system level and RTL descriptions

Cited by 23 publications

References 9 publications

VeriTrust: Verification for Hardware Trust

VeriTrust: Verification for Hardware Trust

An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization

Debugging HDL designs based on functional equivalences with high-level specifications

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