VeriTrust: Verification for Hardware Trust

Zhang, Jie; Yuan, Feng; Wei, Lingxiao; Liu, Yannan; Xu, Qiang

doi:10.1109/tcad.2015.2422836

Cited by 168 publications

(125 citation statements)

References 31 publications

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“…Notice that all these St-D Trojans have a very low value 5. Not all of the benchmarks from TrustHub are listed in TABLE 1, because some of them have no payload, such as RS232-T200.…”

Section: Characterizing Trusthub Benchmarksmentioning

confidence: 99%

“…Recent works have mostly focused on detection [17] and identification schemes [18], which assess to what extent the pieces of hardware may be vulnerable, and how related trojans can be classified. State of the art HT detection schemes include UCI [2], VeriTrust [5], FANCI [6] and DeTrust [8]. Typically, HT detection techniques only show their detection capabilities for HTs from the TrustHub benchmarks suite, in which all trojans are explicitly triggered.…”

Section: Related Workmentioning

confidence: 99%

“…However later works [3], [4] showed how to design HTs which can defeat the UCI detection scheme. Zhang et al [5] and Waksman et al [6] proposed detection schemes called VeriTrust and FANCI respectively and showed that they can detect all HTs from the TrustHub [7] benchmark suite. Yet again, the most recent technique called DeTrust [8] introduces new Trojan designs which can evade both VeriTrust and FANCI.…”

Section: Introductionmentioning

confidence: 99%

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Advancing the state-of-the-art in hardware Trojans design

Haider

Jin

Dijk

2017

2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)

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Abstract-Electronic Design Automation (EDA) industry heavily reuses third party IP cores. These IP cores are vulnerable to insertion of Hardware Trojans (HTs) at design time by third party IP core providers or by malicious insiders in the design team. State of the art research has shown that existing HT detection techniques, which claim to detect all publicly available HT benchmarks, can still be defeated by carefully designing new sophisticated HTs. The reason being that these techniques consider the HT landscape to be limited only to the publicly known HT benchmarks, or other similar (simple) HTs. However the adversary is not limited to these HTs and may devise new HT design principles to bypass these countermeasures. In this paper, we discover certain crucial properties of HTs which lead to the definition of an exponentially large class of Deterministic Hardware Trojans H D that an adversary can (but is not limited to) design. The discovered properties serve as HT design principles, based on which we design a new HT called XOR-LFSR and present it as a 'proof-of-concept' example from the class H D . These design principles help us understand the tremendous ways an adversary has to design a HT, and show that the existing publicly known HT benchmarks are just the tip of the iceberg on this huge landscape. This work, therefore, stresses that instead of guaranteeing a certain (low) false negative rate for a small constant set of publicly known HTs, a rigorous HT detection tool should take into account these newly discovered HT design principles and hence guarantee the detection of an exponentially large class (exponential in number of wires in IP core) of HTs with negligible false negative rate.

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“…Notice that all these St-D Trojans have a very low value 5. Not all of the benchmarks from TrustHub are listed in TABLE 1, because some of them have no payload, such as RS232-T200.…”

Section: Characterizing Trusthub Benchmarksmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Advancing the state-of-the-art in hardware Trojans design

Haider

Jin

Dijk

2017

2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)

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“…Since CAD tools have complete information of the entire chip design, it is possible for them to strategically insert Trojans such that the Trojan detection circuitry cannot detect them (e.g., a Trojan is inserted in both the main function and in the OCP such that predicted check bits and actual check bits are still equal). Verification-based methods for detecting Trojans can be used [14] [104] but are prone to false-negatives (i.e., the Trojan may not be detected). It is likely that all fabricated chips will contain such Trojans; thus, these Trojans can be detected by destructively testing a few chips after fabrication (Section VII.…”

Section: Prevention Of Cad Tool Attacksmentioning

confidence: 99%

TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits

Ganesan

et al. 2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-There are increasing concerns about possible malicious modifications of integrated circuits (ICs) used in critical applications. Such attacks are often referred to as hardware Trojans. While many techniques focus on hardware Trojan detection during IC testing, it is still possible for attacks to go undetected. Using a combination of new design techniques and new memory technologies, we present a new approach that detects a wide variety of hardware Trojans during IC testing and also during system operation in the field. Our approach can also prevent a wide variety of attacks during synthesis, place-and-route, and fabrication of ICs. It can be applied to any digital system, and can be tuned for both traditional and split-manufacturing methods. We demonstrate its applicability for both ASICs and FPGAs. Using fabricated test chips with Trojan emulation capabilities and also using simulations, we demonstrate: 1. The area and power costs of our approach can range between 7.4-165% and 0.07-60%, respectively, depending on the design and the attacks targeted; 2. The speed impact can be minimal (close to 0%); 3. Our approach can detect 99.998% of Trojans (emulated using test chips) that do not require detailed knowledge of the design being attacked; 4. Our approach can prevent 99.98% of specific attacks (simulated) that utilize detailed knowledge of the design being attacked (e.g., through reverse-engineering). 5. Our approach never produces any false positives, i.e., it does not report attacks when the IC operates correctly. I. INTRODUCTION HERE is growing concern about the trustworthiness of integrated circuits (ICs). If an untrusted party fabricates an IC, there is potential for an adversary to insert a malicious hardware Trojan [1], an unauthorized modification of the IC resulting in incorrect functionality and/or sensitive data being exposed [2]. These include (but are not limited to) [3]: a) Modification of functional behavior through logic changes: Index TermsFor example, extra logic gates may be inserted to force an incorrect logic value on a wire at some (arbitrary) point in time (Fig. 1a) [2]. b) Electrical modification: For example, extra capacitive loading may be placed on a circuit path to alter timing characteristics of the IC (Fig. 1b) [2]. c) Reliability degradation: For example, aging of transistors (e.g., Negative Bias Temperature Instability (NBTI)) may be accelerated, degrading reliability ( Fig. 1c) [4]. A hardware Trojan is detected when we report malicious modifications to an IC. A hardware Trojan is prevented when Manuscript received January 9, 2015; revised May 8, 2015; accepted July 20, 2015. Work supported by IARPA Trusted Integrated Chips (TIC) Program. All authors are with Dept. of Electrical Engineering, Stanford University, Stanford, CA 94305 USA (e-mail: tonyfwu@stanford.edu). S. Mitra is also with Dept. of Computer Science, Stanford University.we stop a hardware Trojan from being inserted. Part of the challenge in detecting or preventing hardware Trojans arises from the fact that...

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“…On the other hand, pre-silicon design methods often detect HTs on gated level netlists, which can be categorized into two types: the dynamic and static detection. Dynamic detection techniques [3,4,5,6] generally judge a circuit according to the activation of HT parts. However, HTs are often latent and rarely activated under ordinary functional verification constrains thus hard to discover.…”

Section: Introductionmentioning

confidence: 99%

Hardware Trojans classification based on controllability and observability in gate-level netlist

Xie

Sun

Chen

et al. 2017

IEICE Electron. Express

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This paper presents a hardware Trojan classification method that performs a static analysis in gate-level netlist. Based on the controllability and observability characteristics extracted in a circuit, the nets are clustered into two groups with the k-means method. Then inter-cluster distance is measured and taken as the major feature for Trojan identification. By combined with three other features in terms of circuit scale statistic number, a complementary representation of Trojan circuits is constructed. Finally, a support vector machine classifier is trained to distinguish the Trojan circuits from genuine circuits. Experimental results on Trust-HUB benchmarks demonstrate that our method can achieve up to 100% true positive rate.

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VeriTrust: Verification for Hardware Trust

Cited by 168 publications

References 31 publications

Advancing the state-of-the-art in hardware Trojans design

Advancing the state-of-the-art in hardware Trojans design

TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits

Hardware Trojans classification based on controllability and observability in gate-level netlist

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