Automatic architecture refinement techniques for customizing processing elements

Gorjiara, Bita; Gajski, Daniel D.

doi:10.1145/1391469.1391571

Cited by 18 publications

(11 citation statements)

References 12 publications

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“…However, external don't-cares were not used in the optimization. Gorjiara and Gajski [2008] proposed a framework to generate customized circuits and showed that those circuits are much more power efficient than the original versions. Their work demonstrated that IP customization can be extremely useful.…”

Section: Prior Work On Synthesis With Don't-caresmentioning

confidence: 99%

Logic synthesis and circuit customization using extensive external don't-cares

Chang

Bertacco

Markov

et al. 2010

ACM Trans. Des. Autom. Electron. Syst.

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Traditional digital circuit synthesis flows start from an HDL behavioral definition and assume that circuit functions are almost completely defined, making don't-care conditions rare. However, recent design methodologies do not always satisfy these assumptions. For instance, third-party IP blocks used in a system-on-chip are often over-designed for the requirements at hand. By focusing only on the input combinations occurring in a specific application, one could resynthesize the system to greatly reduce its area and power consumption. Therefore we extend modern digital synthesis with a novel technique, called SWEDE, that makes use of extensive external don't-cares. In addition, we utilize such don't-cares present implicitly in existing simulation-based verification environments for circuit customization. Experiments indicate that SWEDE scales to large ICs with half-million input vectors and handles practical cases well.

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Section: Prior Work On Synthesis With Don't-caresmentioning

confidence: 99%

Logic synthesis and circuit customization using extensive external don't-cares

Chang

Bertacco

Markov

et al. 2010

ACM Trans. Des. Autom. Electron. Syst.

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“…There are some related projects that more or less share the same point of view as the FlexSoC scheme; the No-InstructionSet-Computer (NISC) project [12] comes closest in concept. In this work, only control signals of the local interconnect paths between processing elements in the execution stage or the register file are investigated, and utilized according to the application profile.…”

Section: Related Workmentioning

confidence: 99%

Design space exploration for an embedded processor with flexible datapath interconnect

Hoang

Jalmbrant

Hagopian

et al. 2010

ASAP 2010 - 21st IEEE International Conference on Application-Specific Systems, Architectures and Processors

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The design of an embedded processor is dependent on the application domain. Traditionally, design solutions specific to an application domain have been available in three forms: VLIW-based DSP processors, ASICs and FPGAs; each respectively offering generality of application domain, energy efficiency and flexibility. However, while matching the application domain to the resources needed, the design space becomes huge. We present FlexTools, a tool framework built around the FlexCore architecture to evaluate performance and energy efficiency for different applications. Here we demonstrate FlexTools for design space exploration with a focus on the data-routing flexibility of the FlexCore processor, in search of energy-efficient interconnect configurations that are both cycle-count and hardware efficient. Evaluation results suggest that a well-optimized instance of a 65-nm multiplier-extended FlexCore processor datapath, obtained using FlexTools, executes nine integer EEMBC benchmarks with a 15% cycle count reduction and dissipates 17% less energy than a reference MIPS datapath.

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“…Average power saving reaches 13% on FPGA and 6% on ASIC compared to EXP_3. 7 For comprehensive comparison of the resource usage, we enforce multipliers to be implemented using logic elements, not DSP blocks, with FPGA targets. 8 depending on the values of coefficients C u , C v .…”

Section: -Dimension Discrete Cosine Transformmentioning

confidence: 99%

“…To handle this complexity increase and the "time to market" pressure, design methodologies based on High-Level Synthesis (HLS) can be used [3]. High-level synthesis [4][5][6][7][8] is analogous to software compilation transposed to the hardware domain. From an algorithmic behavior of the specification, HLS tools automate the design process and generate an RTL architecture taking into account designer-specified constraints.…”

Section: Introductionmentioning

confidence: 99%

Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis

Gal¹,

Casseau²

2010

J Sign Process Syst

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International audienceMultimedia applications such as video and image processing are often characterized as computation intensive applications. For these applications the word-length of data and instructions is different throughout the application. Generating hardware architectures is not a straightforward task since it requires a deep word-length analysis in order to properly determine what hardware resources are needed. In this paper we suggest an automated design methodology based on high-level synthesis which takes care of data word- length and interconnection resource cost in order to generate area and power efficient fixed-point architectures for DSP applications. Both ASIC and FPGA technologies are targeted. Experimental results show that our proposed approach reduces area by 6% to 42% on FPGA technology and by 9% to 48 % on ASIC compared to previous approaches. Power saving can reach up to 44% on FPGA technology and 36% on ASIC

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Automatic architecture refinement techniques for customizing processing elements

Cited by 18 publications

References 12 publications

Logic synthesis and circuit customization using extensive external don't-cares

Logic synthesis and circuit customization using extensive external don't-cares

Design space exploration for an embedded processor with flexible datapath interconnect

Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis

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