Design space exploration for an embedded processor with flexible datapath interconnect

Abstract

The design of an embedded processor is dependent on the application domain. Traditionally, design solutions specific to an application domain have been available in three forms: VLIW-based DSP processors, ASICs and FPGAs; each respectively offering generality of application domain, energy efficiency and flexibility. However, while matching the application domain to the resources needed, the design space becomes huge. We present FlexTools, a tool framework built around the FlexCore architecture to evaluate performance and energy efficiency for different applications. Here we demonstrate FlexTools for design space exploration with a focus on the data-routing flexibility of the FlexCore processor, in search of energy-efficient interconnect configurations that are both cycle-count and hardware efficient. Evaluation results suggest that a well-optimized instance of a 65-nm multiplier-extended FlexCore processor datapath, obtained using FlexTools, executes nine integer EEMBC benchmarks with a 15% cycle count reduction and dissipates 17% less energy than a reference MIPS datapath.

Heuristics for greedy transport triggered architecture interconnect exploration

“…After these improvements, TTAs might become preferable to VLIWs in terms of code density, at least in dense inner loops. Moreover, we are experimenting with pruning bypass connections using an optimization pass similar to [12]. This might yield noticeable energy savings since the IC is on most critical paths.…”

“…Hoang et al use design space exploration to prune the IC network in the FlexCore exposed-datapath architecture [12]. The crossbar IC of FlexCore is similar to our VLIW-TTA starting point.…”

“…Pruning bypass connections as in [12] is an unsatisfactory reduction step from this starting point since it has little effect on either issue. We instead shrink the baseline in by merging buses: we select two buses that are infrequently active on the same clock cycle, and combine them into a single bus with the connections of both.…”

Multi-objective aware design flow for coarse-grained systems on chip

“…If the exploration cycles for the time being are excluded from consideration, some of the design space exploration (DSE) flows mainly focus on one certain objective [3], [6], [19], [20] while some others concern more [1], [2], [7], [14]- [18], [21], [22]. L. Bossuet, G. Gogniat and J.L.…”

“…As memory system is often a critical component for multiprocessor systems, [6] describes a fast, accurate technique to estimate an application's average memory latency on a set of memory hierarchies. [19] introduces FlexTools, a tool framework built around the FlexCore architecture to evaluate the system performance with special attention on energy efficiency for different applications. [3] explores algorithm partitioning and system architectures for exploitation of both data and task-level parallelism and include in their study the parameter of different types of memory architectures offered on an FPGA.…”