Automated test generation and test point selection for specification test of analog circuits

Halder, Arnab; Chatterjee, Abhijit

doi:10.1109/isqed.2004.1283707

Cited by 10 publications

(4 citation statements)

References 16 publications

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“…The problem of test points selection has already been addressed and solved in many works such as [7] [8]. More specifically, a co-optimization of the input stimuli and the selection of test points is formulated in [18]. However, instead of posing the optimization problem as a maximization of the fault coverage or a minimization of the tests set as it is usually done, the problem is set as a multiobjective optimization :…”

Section: B Optimization Problemmentioning

confidence: 99%

Automated testing of mixed-signal integrated circuits by topology modification

Coyette

Esen

Vanhooren

et al. 2015

2015 IEEE 33rd VLSI Test Symposium (VTS)

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A general method is proposed to automatically generate a DfT solution aiming at the detection of catastrophic faults in analog and mixed-signal integrated circuits. The approach consists in modifying the topology of the circuit by pulling up (down) nodes and then probing differentiating node voltages. The method generates a set of optimal hardware implementations addressing the multi-objective problem such that the fault coverage is maximized and the silicon overhead is minimized. The new method was applied to a real-case industrial circuit, demonstrating a nearly 100 percent coverage at the expense of an area increase of about 5 percent.

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Section: B Optimization Problemmentioning

confidence: 99%

Automated testing of mixed-signal integrated circuits by topology modification

Coyette

Esen

Vanhooren

et al. 2015

2015 IEEE 33rd VLSI Test Symposium (VTS)

View full text Add to dashboard Cite

show abstract

“…Similarly, the simulation models for complicated RF systems are generally very complex and time consuming for repeated Monte Carlo simulations necessary during the alternate test stimulus generation process. Although the use of high-level behavioral device models have been proposed in the past to improve simulation speed, the complexity of these models limit the search space [16] or forces computationally cheaper yet sub-optimal greedy search [17].…”

Section: Motivation and Key Contributionsmentioning

confidence: 99%

Alternate Test of RF Front Ends with IP Constraints: Frequency Domain Test Generation and Validation

Akbay

Torres

Rumer

et al. 2006

2006 IEEE International Test Conference

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This paper summarizes an alternate test methodology that enables significant reduction in testing time and tester complexity for RF circuits without the need for low-level simulation models. Traditionally, alternate test makes use of circuit and process-level models to analyze the sensitivity of datasheet specifications to the variations in process parameters. In this paper, we demonstrate a "gray-box" approach by creating a high-level simulation model from datasheet information and simple hardware measurements. This model is used together with a customized behavioral simulator to enable efficient search of an alternate test stimulus that is optimal in terms of tester constraints, test time and specification prediction accuracy. The specific example is a third party RF front-end chip, for which 13 specifications including S-parameters, intermodulation products and noise figures are measured with both conventional and alternate methods. The results are compared in terms of testing time, tester cost and accuracy.

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“…Unlike other testing approaches where numerous and most appropriate testing points have to be selected, observed, and captured signals processed, [13], the number of OBT test points is one, i.e. the oscillator"s output.…”

Section: Introductionmentioning

confidence: 99%

Oscillation-based testing method for detecting switch faults in High-Q SC biquad filters

Milic

Litovski

2015

FACTA U EE

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Testing switched capacitor circuits is a challenge due to the diversity of the possible faults. A special problem encountered is the synthesis of the test signal that will control and make the fault-effect observable at the test point. The oscillation based method which was adopted for testing in these proceedings resolves that important issue in its nature. Here we discuss the properties of the method and the conditions to be fulfilled in order to implement it in the right way. To achieve that, we have resolved the problem of synthesis of the positive feedback circuit and the choice of a proper model of the operational amplifier. In that way, a realistic foundation to the testing process was generated. A second order notch cell was chosen as a case-study. Fault dictionaries were developed related to the catastrophic faults of the switches used within the cell. The results reported here are a continuation of our previous work and are complimentary to some other already published.

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Automated test generation and test point selection for specification test of analog circuits

Cited by 10 publications

References 16 publications

Automated testing of mixed-signal integrated circuits by topology modification

Automated testing of mixed-signal integrated circuits by topology modification

Alternate Test of RF Front Ends with IP Constraints: Frequency Domain Test Generation and Validation

Oscillation-based testing method for detecting switch faults in High-Q SC biquad filters

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