Automated Robust Design and Optimization of Integrated Circuits by Means of Penalty Functions

Abstract

Abstract:The ever-shorter time-to-market calls for efficient robust IC design algorithms. Robust circuits satisfy all design requirements across a range of operating conditions and manufacturing process variations. In the paper we propose an automated robust IC design and optimization process derived from the design algorithms utilized manually by experienced analog IC designers. We achieve this by transforming the robust design and optimization problem into a constrained optimization problem using tradeoff planes and penalty functions. We illustrate the method on a robust differential amplifier design problem. Circuits resulting from several different optimization runs show that a computer can not only improve existing circuit designs but it can also size a circuit with very little initial knowledge. The resulting circuits have comparable or even superior performance to humanly designed circuits. The method could easily take advantage of parallel processing but is still efficient enough to be run on a single computer.

Analogue integrated circuit sizing with several optimization runs using heuristics for setting initial points

“…The information about design robustness is included into the cost function. Since the design is considered robust if it performs well in all relevant corner points, the circuit characteristics are evaluated for those corner points as well [12] and the corresponding terms are added to the cost function. Therefore in each iteration of the optimization procedure the required circuit analyses have to be done for the nominal operating and process conditions and the relevant corner points.…”

“…A statistical model of the cost function was presented. The construction of cost function itself [12] is beyond the scope of this paper.…”

“…Recently numerous papers (e.g. [12], [18]- [23]) are addressing the sizing problem from different aspects like process and operating tolerances, mismatch, yield and robustness.…”

“…Circuit sizing is an optimization process by its nature and one can find quite extensive literature in this area. Sizing of nominal circuits was considered in [5]- [6], £ Faculty of Electrical Engineering, University of Ljubljana, Tržaška cesta 25, 1001 Ljubljana, Slovenia e-mails: janez.puhan, arpad.buermen, tadej.tuma @fe.uni-lj.si sizing problems accounting for parameter tolerances (parameter centering) were addressed in [7]- [9], and worst-case optimization in [10]- [12]. Various optimization tools were developed, like equation based GPCAD [13], which uses geometric programming formulation of an optimization problem [14] on predefined posynomial equations, AMG [15], utilising a symbolic simulator [16] to obtain circuit equations, and the simulation based ASTRX/OBLX [17].…”

Combined simplex-trust-region optimization algorithm for automated IC design

“…The CF was constructed according to [8] and is not the subject of this paper where we are interested only in the optimization algorithm itself. The performance of the algorithm can be assessed through the final CF value and the number of CF evaluations that are needed to reach this value.…”