Analogue integrated circuit sizing with several optimization runs using heuristics for setting initial points

Abstract

Circuit sizing (e.g. determining MOSFET channel widths and lengths which result in the most appropriate and robust circuit) is an optimization process. When it is completed, there always remains a dilemma, whether a better solution exists. With different starting points one can arrive at different local minima. A heuristic process, consisting of many optimization runs started from different initial points, is proposed. It tries to find another local minimum of the cost function in every run and thus reveals some additional information about the circuit. The mathematical background of the algorithm used is described. Finally, the heuristic algorithm is tested on some real integrated operating amplifier designs. The results show, that from the cost function's point of view surprisingly many equivalent solutions exists.Proportinner les circuits, c'està dire, détérminer la largeur et la longueur des cannaux MOSFET, qui résultent en le circuit le plus approprié et le plus robuste, est sans doute un procès d'optimisation. Mais, le procès terminé, il y reste toujours une dilèmme, s'il on y existe pas une solutions meilleure. Si on prend les points du départ différents, on peut arriver aux minima locaux très divers. L'article propose de mettre en oeuvre un procès heuristique, en train duquel on fait marcher l'optimisation plusieures fois déterminant les points du départ très différents. Pendant chaque marche d'optimisation on essaie de trouver un minimum local d'une fonction de critère et ainsi obtenir des informations supplémentaires sur le circuit. L'article engage le fond mathématique de l'argorithme utilisé. Enfin, l'argorithme heuristique est mis sous l'épreuve en cadre des dessins réels intégrés d'amplificateur opérant. Le résultat est surprénant; du point du vu de la fonction de critère, il y existe beaucoup des solutionséquivalentes.

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