Automated modeling and emulation of interconnect designs for many-core chip multiprocessors

Ihrig, Colin J.; Melhem, Rami; Jones, Alex K.

doi:10.1145/1837274.1837383

Cited by 3 publications

(2 citation statements)

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“…The bandwidth measured for the system was of 36 Mbytes/s including the complete transaction necessary to code, send and decode a message. Ihrig et al, (2010) [19] present a tool for design flux automation called ACME which makes it easy to emulate hardware in new interconnection networks for wide multicore designs. The tools are intended to computer and network designers, which possess the digital design knowledge but do not feel comfortable with hardware description languages and synthesis fluxes.…”

Section: Figure 3 System Prototype With 4 Xilinx Microblaze In Netwomentioning

confidence: 99%

Platforms and Applications in Hardware Security: Trends and Challenges

Moreno¹

2013

IJSIA

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Section: Figure 3 System Prototype With 4 Xilinx Microblaze In Netwomentioning

confidence: 99%

Platforms and Applications in Hardware Security: Trends and Challenges

Moreno¹

2013

IJSIA

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“…Another growing area of simulation development is the use of Field-Programmable Gate Arrays (FPGAs) as co-processors [7,8,9,10]. FPGAs have become popular because they can take advantage of the fine-grained parallelism between hardware structures.…”

Section: Introductionmentioning

confidence: 99%

Scalable Multi-cache Simulation Using GPUs

Moeng

Cho

Melhem

2011

2011 IEEE 19th Annual International Symposium on Modelling, Analysis, and Simulation of Computer and Telecommunication Systems

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Software simulation is the primary tool used for evaluation of processor design. Simulation offers better accuracy than analytical models and is an important evaluation step before actually fabricating a chip. Unfortunately, simulator speeds are slow-a conventional cycle-accurate simulator will be unable to keep up with increasing core counts in modern processor design.Parallel simulation is one method for improving simulation speeds. Two major areas of parallel simulation research are multithreaded simulators and FPGAs as simulation accelerators. Multithreaded simulators can only extract coarse-grained parallelism and must sacrifice accuracy in order to scale well. FPGA-based simulators can extract fine-grained parallelism, but are expensive and difficult to program.We propose using GPUs for architectural simulation, which can take advantage of a high degree of fine-grained parallelism. In addition, they are inexpensive and easier to program compared to FPGAs. To demonstrate our ideas, we implement a tracedriven many-cache simulator using NVIDIA's CUDA toolkit. GPU-accelerated cache simulation displays remarkable scaling with number of simulated caches when compared to serial CPUonly simulation.

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