Scalable Multi-cache Simulation Using GPUs

Moeng, Michael; Cho, Sangyeun; Melhem, Rami

doi:10.1109/mascots.2011.24

Cited by 4 publications

(2 citation statements)

References 17 publications

(37 reference statements)

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“…Traces have also been used to build more realistic cache simulators [8,11,14]. Moeng et al [14] proposed the use of GPUs to accelerate a trace-based cache simulator conceived to study the cache coherence in multithreaded workloads and multilevel cache implementations. The information is collected once using a functional simulator and a trace of events is generated.…”

Section: Related Workmentioning

confidence: 99%

A trace-driven methodology to evaluate and optimize memory management services of distributed operating systems for lightweight manycores

Podestá

Penna

Uller

et al. 2021

Proceedings of the 36th Annual ACM Symposium on Applied Computing

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Lightweight manycores belong to a new class of emerging lowpower processors for the Exascale era. These processors present several challenges for the development of applications, such as distributed memory architecture, limited amount of on-chip memory and no cache coherence. Recently, distributed Operating Systems (OSs) have been proposed to address these challenges in a transparent way. In these systems, different OS services are deployed across the processor cores, being the memory management service one of the most important ones. However, the intrinsic characteristics and memory limitations of lightweight manycores bring several challenges to the design, implementation and future optimizations of memory management services. In this work, we propose a tracedriven methodology to evaluate and optimize features of a memory management service of distributed OSs for lightweight manycores. By using a compact representation of the page access pattern of the applications, our methodology is capable of mimicking the memory access pattern of the original applications on the target distributed OS running on a lightweight manycore. We integrated our methodology in a distributed OS (Nanvix) and validated it using three applications from a specific benchmark for lightweight manycores (CAP Bench). Then, we applied our methodology to carry out a case study using a software-managed cache implementation available in Nanvix. Our methodology enabled us to evaluate different page replacement policies on Kalray MPPA-256, even without the required support from the architecture to implement them. CCS CONCEPTS• Computer systems organization → System on a chip; Very long instruction word; Multiple instruction, multiple data; Parallel architectures;

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Section: Related Workmentioning

confidence: 99%

A trace-driven methodology to evaluate and optimize memory management services of distributed operating systems for lightweight manycores

Podestá

Penna

Uller

et al. 2021

Proceedings of the 36th Annual ACM Symposium on Applied Computing

View full text Add to dashboard Cite

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“…GPUs lay the foundation for improving the performance of a wide range of different types of simulations, including simulations of physical processes [9], computer architectures [10], vehicular networks [11], Monte Carlo simulations [12], etc. A comprehensive survey by Owens et al [13] gives an overview of the subject.…”

Section: Related Workmentioning

confidence: 99%

Multi-level Parallelism for Time- and Cost-Efficient Parallel Discrete Event Simulation on GPUs

Kunz

Schemmel

Gross

et al. 2012

2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation

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Abstract-Developing complex technical systems requires a systematic exploration of the given design space in order to identify optimal system configurations. However, studying the effects and interactions of even a small number of system parameters often requires an extensive number of simulation runs. This in turn results in excessive runtime demands which severely hamper thorough design space explorations.In this paper, we present a parallel discrete event simulation scheme that enables cost-and time-efficient execution of large scale parameter studies on GPUs. In order to efficiently accommodate the stream-processing paradigm of GPUs, our parallelization scheme exploits two orthogonal levels of parallelism: External parallelism among the inherently independent simulations of a parameter study and internal parallelism among independent events within each individual simulation of a parameter study. Specifically, we design an event aggregation strategy based on external parallelism that generates workloads suitable for GPUs. In addition, we define a pipelined event execution mechanism based on internal parallelism to hide the transfer latencies between host-and GPU-memory. We analyze the performance characteristics of our parallelization scheme by means of a prototype implementation and show a 25-fold performance improvement over purely CPU-based execution.

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