Automated generation of SPICE characterization test masks and test databases

Kasel, L.; McAndrew, Colin C.; Drennan, P.G.; Davis, W.F.; Ida, R.

doi:10.1109/icmts.1999.766219

Cited by 9 publications

(2 citation statements)

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“…Kumar et al [8] proposed a test chip design environment, which is based on commercial layout tool and uses in-house software to link with parametric test system. L. Kasel et al [9] presented a platform, which automatically generates test mask and measurement databases for SPICE model characterization. To fulfill the requirement of using multiple test vehicles for process development, one of the criteria is to provide the design consistency of test structures between the various test vehicle design versions and technology nodes.…”

Section: Introductionmentioning

confidence: 99%

Library-based process test vehicle design framework

Doong

Hung

et al. 2003

SPIE Proceedings

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This work describes a test vehicle design framework, which minimizes the discrepancy among design rule set, test structure design and testing plan. The framework is composed of the symbolic design rule set, Parameterized-Device, test structure generator, and test vehicle generator. An approach for simplification and consolidation of test structure is proposed to derive the concise test structure library. Finally, implementation of test vehicle is presented.

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Section: Introductionmentioning

confidence: 99%

Library-based process test vehicle design framework

Doong

Hung

et al. 2003

SPIE Proceedings

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“…Kumar et al [12] proposed a test chip design environment based on commercial layout tools and used in-house software to link the design to the parametric test system. Kasel et al [13] presented a platform that can automatically generate test masks and measurement databases for SPICE model characterization. Nagorski et al [14] proposed a documentation methodology using a specific file format as the layout design input and test chip documentation for the design automation.…”

mentioning

confidence: 99%

Infrastructure Development and Integration of Electrical-Based Dimensional Process Window Checking

Doong

Huang

Chu

et al. 2004

IEEE Trans. Semicond. Manufact.

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This study aims to provide an integrated infrastructure for electrical-based dimensional process-window checking. The proposed infrastructure is comprised of design tools, testing programs, and analytical tools, providing an automatic and hierarchical test vehicle design flow from the design of the test structure to the analysis of the electrical test data. Symbolic parameter representation is adopted to describe the relationship between design rules and test structure parameters. This integrated infrastructure also provides a specific capability for controlling local/global layout geometry and pattern density, thereby fulfilling deep sub-micron design criteria. With the aid of this design platform, discrepancies between the design rule set, test structure design, and the testing plan are minimized. Using the function-independent Test Structure Design Intellectual Property (TSD-IP) provided by this infrastructure, the process-window is quantitatively characterized as the electrical parameters. A cross-generation test vehicle (130-nm/90-nm nodes), used for evaluating any overlay shifts and variations in critical dimensions across the intra-and interphoto fields, has been developed to demonstrate the proposed design infrastructure.Index Terms-Automatic test equipment, design automation, full-loop process, integrated circuit layout, short-loop process.

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