Authenticated encryption on FPGAs from the static part to the reconfigurable part

Abstract

Recently, techniques have been invented to combine encryption and authentication into a single algorithm which is called Authenticated Encryption (AE). Combining these two security services in hardware produces smaller area compared to two separate algorithms. AE is implemented in the static part of the FPGA (FPGA silicon) in order to secure the reconfiguration process to ensure the confidentiality and integrity of the bitstream. Also, it is used in the reconfigurable part of the FPGA to support applications which need security requirements like Virtual Private Networks (VPNs). This paper presents two different directions for implementing AE cores on FPGAs. First, we present efficient ASIC implementations of AE algorithms, Counter with Cipher Block Chaining Mode (CCM) and Galois Counter Mode (GCM), which are used in the static part of the FPGA in order to secure the reconfiguration process. Our focus on state of the art algorithms for efficient implementations leads to propose efficient compact architectures in order to be used for FPGA bitstream security. Presented ASIC architectures were evaluated by using 90 and 130 nm technologies. Second, high-throughput GCM architectures are implemented in the reconfigurable part of the FPGA by taking the advantage of slow changing key environments like VPNs and embedded memory protection. The proposed architectures were evaluated using Virtex5 and Virtex4 FPGAs. It is shown that the performance of the presented work outperforms the previously reported ones.

AES-GCM and AEGIS: Efficient and High Speed Hardware Implementations

“…Therefore, most of the previous hardware architectures were proposed to support high speed applications. As a result, the pipelined AES was used to perform the encryption task of AES-GCM [4,6,8,9].…”

“…This design proposed by [5] can be used efficiently (smaller area) on FPGAs as the circuit is specialized for H. We integrated this multiplier proposed by [5] with a key-synthesized AES engine in [6] in order to support slow changing key applications like Virtual Private Networks (VPNs). Also, in [6], we proposed a protocol to secure the FPGA reconfiguration to protect the bitstream because it is a key-based bitsream. The disadvantage of this method is the new reconfiguration which must be downloaded on the FPGA in case of changing the key.…”

“…Four different architectures of FPGAs-based AES-GCM have been presented in the open literature [6][7][8][9]. It is clear that these contributions do generally have different challenges related to the performance of their architectures.…”

“…It is clear that these contributions do generally have different challenges related to the performance of their architectures. The performance of our previous architecture [6] is limited because a new reconfiguration is needed in case of changing the key. Also, Zhou et al [8] claimed a throughput improvement to their previous KOA-based GHASH [7] by using pipelined KOA, but we discussed how their method is not efficient for throughput improvement as shown in Eq.…”

“…Hence, no new reconfiguration is needed in case of changing the key unlike our previous architectures in [6].…”