Atomically Flat Silicon Surface and Silicon/Insulator Interface Formation Technologies for (100) Surface Orientation Large-Diameter Wafers Introducing High Performance and Low-Noise Metal–Insulator–Silicon FETs

The importance of Si surface flatness on metal-oxide-semiconductor field-effect transistor (MOSFET) characteristics with ultrathin hafnium oxynitride (HfON) high-k gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering was described. The surface roughness of Si substrate was reduced by Ar/4.9%H 2 annealing utilizing conventional rapid thermal annealing (RTA) system. Si surface root-mean-square (RMS) roughness was well controlled by changing the annealing temperature from 700 to 1000°C. Si surface RMS roughness after 1000°C/1 hr annealing was 0.078 nm for Si(100) and 0.082 nm for Si(110), respectively. Clear dependence of electrical characteristics of MOS diodes such as equivalent oxide thickness (EOT) and leakage current on the surface RMS roughness of Si(100) and Si(110) was observed, and the electrical characteristics were remarkably improved by decreasing of surface RMS roughness. The MOSFET characteristics with HfON gate insulator fabricated on Si(100) substrates after flattening process were also improved.

Section: Introductionmentioning

confidence: 96%

Importance of Si surface flatness to realize high-performance Si devices utilizing ultrathin films with new material system

Ohmi

2014

“…And a small trap density insulator film should be formed above the PD for suppressing the fixed charge generation due to trapping of the carriers excited by high photon energy UV-light. Here, the atomically flat Si surface is formed by annealing a bare Si surface wafer at around 800°C or above in an ultra-pure Ar ambient with a residue H 2 O concentration of 30 ppb or less [20,21,22]. By this process, a flat Si surface formed by atomic terrace and mono-atomic layer steps are obtained [20].…”

Section: Introductionmentioning

confidence: 99%

“…Here, the atomically flat Si surface is formed by annealing a bare Si surface wafer at around 800°C or above in an ultra-pure Ar ambient with a residue H 2 O concentration of 30 ppb or less [20,21,22]. By this process, a flat Si surface formed by atomic terrace and mono-atomic layer steps are obtained [20]. In addition, by an alkali-free wet cleaning process in dark ambient condition for bare Si wafer to suppress the local Si etching and by an oxygen radical oxidation process with isotropic oxidation reaction, the atomic flatness level is maintained through the device fabrication process [20,21].…”

Section: Introductionmentioning

confidence: 99%

“…By this process, a flat Si surface formed by atomic terrace and mono-atomic layer steps are obtained [20]. In addition, by an alkali-free wet cleaning process in dark ambient condition for bare Si wafer to suppress the local Si etching and by an oxygen radical oxidation process with isotropic oxidation reaction, the atomic flatness level is maintained through the device fabrication process [20,21]. through 7 nm thick oxide film.…”

Section: Introductionmentioning

confidence: 99%

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Si image sensors with wide spectral response and high robustness to ultraviolet light exposure

Kuroda

Sugawa

2014

Self Cite

Si image sensors with a wide spectral response range and a high robustness to ultraviolet light exposure based on flattened Si surface are described in this paper. A photodiode (PD) fabrication technology is developed to form a thin surface high concentration layer with steep dopant profile on flattened Si surface. Due to this, PDs with a wide spectral response ranging from 200 to 1000 nm is achieved with almost 100% internal quantum efficiency to ultraviolet light (UV-light) waveband. In addition, high robustness of light sensitivity and dark current toward UV-light exposure is obtained. The developed technology is applied to in-pixel buried PDs of photodiode arrays and a CMOS image sensor. The advanced performances of fabricated sensors are verified with experimental results.

“…Recently many institutions have reported that MOSFETs with atomically flat interface between Si(100) and gate insulator show higher performances than those with conventional devices [8,9,10]. It has been known that the carrier mobility improved by flattening the interface between Si and gate insulator, because the carrier scattering caused by the interface roughness is suppressed [10,11].…”

Section: Introductionmentioning

confidence: 99%

Impact of Si surface roughness on MOSFET characteristics with ultrathin HfON gate insulator formed by ECR plasma sputtering

Han

Ohmi

2013

In this paper, the impact of Si surface roughness on metal oxide semiconductor field effect transistor (MOSFET) characteristics with ultrathin hafnium oxynitride (HfON) gate insulator formed by electron cyclotron resonance (ECR) sputtering was investigated. The surface roughness of Si substrate was reduced by Ar/4.9%H 2 annealing utilizing conventional rapid thermal annealing (RTA) system. The obtained root-mean-square (RMS) roughness was 0.08 nm (as-cleaned: 0.21 nm). The HfON was formed by 2 nm-thick HfN deposition followed by the Ar/O 2 plasma oxidation. The electrical properties of HfON gate insulator were improved by the reduction of Si surface roughness. It was found that the current drivability of fabricated nMOSFETs was remarkably increased by reduction of Si surface roughness.