Atomic-layer-deposition-assisted ZnO nanoparticles for oxide charge-trap memory thin-film transistors

Abstract

ZnO nanoparticles (NPs) with monolayer structures were prepared by atomic layer deposition (ALD) to use for a charge-trap layer (CTL) for nonvolatile memory thin-film transistors (MTFTs). The optimum ALD temperature of the NP formation was demonstrated to be 160 °C. The size and areal density of the ZnO NPs was estimated to be approximately 33 nm and 4.8 × 10 cm, respectively, when the number of ALD cycles was controlled to be 20. The fabricated MTFTs using a ZnO-NP CTL exhibited typical memory window properties, which are generated by charge-trap/de-trap processes, in their transfer characteristics and the width of the memory window (MW) increased from 0.6 to 18.0 V when the number of ALD cycles increased from 5 to 30. The program characteristics of the MTFT were markedly enhanced by the post-annealing process performed at 180 °C in an oxygen ambient due to the improvements in the interface and bulk qualities of the ZnO NPs. The program/erase (P/E) speed was estimated to be 10 ms at P/E voltages of -14 and 17 V. The memory margin showed no degradation with the lapse in retention time for 2 × 10 s and after the repetitive P/E operations of 7 × 10 cycles.

Improvement of the Charge Retention of a Non-Volatile Memory by a Bandgap-Engineered Charge Trap Layer

“…The threshold voltage of the device shifted in the positive direction. [23][24][25] The MOS device was fabricated with three different CTL as the dielectric layer and deposited 300 nm Al as the metal electrode. The…”

Charge-trap-assisted flexible nonvolatile memory applications using oxide-semiconductor thin-film transistors

“…ZnO or Ag nano-particles have also been introduced for the discrete shape of CTLs to improve memory retention properties. 73,74) Furthermore, variations in the film thicknesses of the Al 2 O 3 tunneling oxide and ZnO CTL have been investigated to clearly figure out the thickness effects on memory device characteristics. 36) New approaches have provided meaningful advances in one or two characteristics among many requirements, but it is very tough to totally enhance and optimize the memory performance of CT-MTFTs.…”

Synergic Impacts of CF4 Plasma Treatment and Post-thermal Annealing on the Nonvolatile Memory Performance of Charge-Trap-Assisted Memory Thin-Film Transistors Using Al–HfO2 Charge Trap and In–Ga–Zn–O Active Channel Layers

“…Amorphous oxide semiconductors (AOSs) have been attracting much attention as active layers to replace polycrystalline silicon channels for advanced three-dimensional device structures due to various advantages such as high mobility, low-temperature compatibility, and grain-boundary-free uniform natures. − Alternatively, charge-trap-assisted memory thin-film transistors (CTM-TFTs) utilizing AOS channels, in which the charges are stored in localized trap sites within the charge-trap layers (CTLs), can be promising candidates as next-generation nonvolatile memories (NVMs), which are featured to have such advantages as a low operating voltage, excellent operational reliabilities, and compatibility with complementary metal oxide semiconductor technology (CMOS). − With the aim of realizing highly functional nonvolatile CTM-TFTs, various strategies, such as the introduction of high-dielectric-constant (high-k) CTLs, − CTL engineering, − and interfacial treatments between the tunneling layer (TL) and CTL, − have been investigated in order to enhance the program/erase (P/E) efficiencies and NVM reliabilities with improving the CTL trap densities and interfacial qualities. Alternatively, the continuous device scaling urges to further reduce the physical thickness of the gate stacks including the CTL and TL, and hence, the conventional CTM devices employing silicon nitride (Si 3 N 4 ) CTLs have faced the critical limit of a trade-off relationship between P/E speed and memory retention time. , Therefore, to overcome this problem and enhance the memory characteristics in terms of charge-trapping efficiency and equivalent oxide thickness (EOT) scaling, we previously demonstrated the NVM characteristics assisted by charge-trap/detrap events of the CTM-TFTs using oxide semiconductor materials, such as ZnO, − ,− In–Ga–Zn–O, (IGZO), and Hf-doped ZnO, as CTLs. Irrespective of successful demonstrations on previously reported CTM-TFTs employing the oxide channel, the choice of oxide semiconductor CTLs needed to be patterned with a double-layered tunneling oxide to avoid chemical damages induced into the channel layer during the patterning process .…”