Asynchronous Techniques for System-on-Chip Design

Abstract

| SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained.Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALSVone based on synchronizer, the other on stoppable clockVare described and analyzed.

Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

“…A complete data transfer should wait about one or two more clock cycles at each transfer through serialized two flip-flops, and the next data transfer cannot start before the previous data transfer is completed [10,14]. To prevent overheads caused by synchronizing with a two-flop synchronizer for all data bits on wide data paths, an asynchronous handshake protocol bundled with such data paths is typically used [12,15]. A speculative synchronizer [16] and a parallel flop synchronizer [17] to alleviate the inherent latency have been presented, but they have failed to perfectly eliminate the latency.…”

“…Lastly, an asynchronous environment does not have any restrictions of the clock, but an asynchronous design technique needs extra handshaking circuits for its finegrained and localized data synchronization [4,12].…”

Neural spiking dynamics in asynchronous digital circuits

“…asynchronous, it can seamlessly integrate with the routing fabric without the necessity to cross timing domains as would be the case in a GALS system. Applying an asynchronous design methodology across the whole system eliminates the need for synchronization circuits and design difficulties such as timing closure [26].…”

Asynchronous logic for high variability nano-CMOS

“…The implementation of the read part presents no difficulty. The set/reset latch can be implemented as cross-coupled nor-gates which do not need relative sizing unlike the implementation with cross-coupled inverters (see [4]). Only the wack needs some attention.…”

“…A worst-case example, where the adversary path contains just one gate, is the Caltech "Q-element" (see [4]) shown in We analyze the isochronic fork (li, li1, li2). Initially, x 2 is true and ro is false.…”