Asynchronous System-on-Chip Interconnect

Bainbridge, J.

doi:10.1007/978-1-4471-0189-5

Cited by 23 publications

(21 citation statements)

References 24 publications

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“…The models of the wires used in our simulations were constructed from 0.5-mm segments. Values for resistance in ohms and capacitance in farads per millimeter length were obtained by postlayout extraction [8].…”

Section: Resultsmentioning

confidence: 99%

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An asynchronous ternary logic signaling system

Felicijan

Furber

2003

IEEE Trans. VLSI Syst.

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Abstract-This paper presents a new approach to an on-chip asynchronous transmission system suitable for next generation asynchronous on-chip networks. It implements multivalued logic to reduce the number of wires and a low-voltage swing for lower dynamic power dissipation. Furthermore, the transmission system described here enjoys fully static design and has zero static power consumption. Two versions of the transmitter circuit and the receiver are described. The proposed signaling scheme is compared to a classical dual-rail signaling system with regard to speed, power consumption, and reliability. The simulation results show that the asynchronous ternary logic signaling (ATLS) system delivers over 70% higher bandwidth per wire and consumes over 50% less power than the dual-rail signaling system on 10-mm-long on-chip interconnection.Index Terms-Communication system signaling, digital CMOS, low-power design, low voltage, multivalued logic.

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Section: Resultsmentioning

confidence: 99%

“…The ATLS system is not intended for conventional bidirectional on-chip buses such as MARBLE [8], but is ideally suited to unidirectional signaling in next generation self-timed networks on a chip such as CHAIN [10] where individual links can employ ATLS on a case-by-case basis.…”

Section: Applicabilitymentioning

confidence: 99%

An asynchronous ternary logic signaling system

Felicijan

Furber

2003

IEEE Trans. VLSI Syst.

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“…Asynchronous On-Chip Buses (OCBs) [12,13] have been proposed for low power GAI. These OCBs enable low latency with small silicon area, as synchronous OCBs [5][6][7][8] widely used in SoC design.…”

Section: Introductionmentioning

confidence: 99%

Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions

Jung

Lee

Jhang

et al. 2007

J VLSI Sign Process Syst Sign Image Video Technol

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In this paper, a novel asynchronous layered interface for a high performance on-chip bus is designed in a Globally Asynchronous Locally Synchronous (GALS) style. The proposed asynchronous layered interface with distributed and modularized control units supports multiple outstanding in-order/out-of-order transactions to achieve high performance. In the layered architecture, extension of an asynchronous layered interface performing complex functions is readily achieved without repeating the implementation of the whole bus interface. Simulations are carried out to measure the performance and power consumption of implemented asynchronous on-chip bus with the proposed asynchronous layered interface. Simulation results demonstrate that throughput of the asynchronous on-chip bus with multiple outstanding out-of-order transactions is increased by 30.9%, while power consumption overhead is 16.1% and area overhead is 56.8%, as compared to the asynchronous on-chip bus with a single outstanding transaction.

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“…The key property of an N-of-M code, guaranteeing its delayinsensitivity, is that every transition from a spacer to a valid combination never passes through another valid combination. Examples of N-of-M codes, e.g., 1-of-4, 3-of-6, 2-of-7, have been used in self-timed systems described in [22], [1].…”

mentioning

confidence: 99%

Design and analysis of a self-timed duplex communication system

Yakovlev

Furber

Krenz

et al. 2004

IEEE Trans. Comput.

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Abstract-Communication-centric design is a key paradigm for systems-on-chips (SoCs), where most computing blocks are predesigned IP cores. Due to the problems with distributing a clock across a large die, future system designs will be more asynchronous or self-timed. For portable, battery-run applications, power and pin efficiency is an important property of a communication system where the cost of a signal transition on a global interconnect is much greater than for internal wires in logic blocks. The paper addresses this issue by designing an asynchronous communication system aimed at power and pin efficiency. Another important issue of SoC design is design productivity. It demands new methods and tools, particularly for designing communication protocols and interconnects. The design of a self-timed communication system is approached employing formal techniques supported by verification and synthesis tools. The protocol is formally specified and verified with respect to deadlockfreedom and delay-insensitivity using a Petri-net-based model-checking tool. A protocol controller has been synthesized by a direct mapping of the Petri net model derived from the protocol specification. The logic implementation was analyzed using the Cadence toolkit. The results of SPICE simulation show the advantages of the direct mapping method compared to logic synthesis.

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Asynchronous System-on-Chip Interconnect

Cited by 23 publications

References 24 publications

An asynchronous ternary logic signaling system

An asynchronous ternary logic signaling system

Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions

Design and analysis of a self-timed duplex communication system

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