Asymmetrically Doped FinFETs for Low-Power Robust SRAMs

Moradi, Farshad; Gupta, Sumeet Kumar; Panagopoulos, Georgios; Wisland, Dag T.; Mahmoodi, Hamid; Roy, Kaushik

doi:10.1109/ted.2011.2169678

Cited by 59 publications

(42 citation statements)

References 23 publications

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“…11.18. Similar to the ADSE FinFETs, AD FinFETs exhibit unequal currents for positive and negative V DS [23]. The current flowing from the terminal with lower doping (i.e.…”

Section: Srams Based On Asymmetrically Doped (Ad) Finfetsmentioning

confidence: 99%

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Low Power Robust FinFET-Based SRAM Design in Scaled Technologies

Gupta

Roy

2014

Circuit Design for Reliability

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FinFETs have emerged as alternatives to conventional bulk MOSFETs in scaled technologies due to superior gate control of the channel, lower short channel effects and higher scalability. However, width quantization in FinFETs constrains the design space of FinFET-based circuits, especially SRAMs in which transistor sizing is critical for the circuit robustness. The adverse effects of width quantization can be mitigated by appropriate device-circuit co-design of FinFETbased memories. This chapter describes some of such techniques with an emphasis on the device-circuit interactions associated with each methodology. The impact of different technology options in FinFETs like gate-underlap, fin orientation, fin height, gate workfunction and independent control of the gates on the stability, power and performance of 6 T SRAMs is discussed.

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“…11.18. Similar to the ADSE FinFETs, AD FinFETs exhibit unequal currents for positive and negative V DS [23]. The current flowing from the terminal with lower doping (i.e.…”

Section: Srams Based On Asymmetrically Doped (Ad) Finfetsmentioning

confidence: 99%

“…During the read operation, the strength of the access transistor reduces, increasing the read stability. During the write operation, higher drive of the [23] access transistors leads to increase in the write-ability. In addition lower cell leakage is achieved at the cost of increase in the access time.…”

Section: Srams Based On Asymmetrically Doped (Ad) Finfetsmentioning

confidence: 99%

Low Power Robust FinFET-Based SRAM Design in Scaled Technologies

Gupta

Roy

2014

Circuit Design for Reliability

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“…In order to improve the robustness (i.e., read/write margins) of SRAM cells, FinFET-based SRAMs have been proposed [5] [6]. FinFET devices are currently one of the most effective ways to reduce short channel effects.…”

Section: Introductionmentioning

confidence: 99%

A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations

Shafaei

Chen

Wang

et al. 2015

The 20th Asia and South Pacific Design Automation Conference

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A cross-layer framework (spanning device and circuit levels) is presented for designing robust and energy-efficient SRAM cells, made of deeply-scaled FinFET devices. In particular, 7nm FinFET devices are designed and simulated by using Synopsys TCAD tool suite, Sentaurus. Next, 6T and 8T SRAM cells, which are composed of these devices, are designed and optimized. To enhance the cell stability and reduce leakage energy consumption, the dual (i.e., front and back) gate control feature of FinFETs is exploited. This is, however, done without requiring any external signal to drive the back gates of the FinFET devices. Subsequently, the effect of process variations on the aforesaid SRAMs is investigated and steps are presented to protect the cells against these variations. More precisely, the SRAM cells are first designed to minimize the expected energy consumption (per clock cycle) subject to the non-destructive read and successful write requirements under worst-case process corner conditions. These SRAM cells, which are overly pessimistic, are then refined by selectively adjusting some transistor sizes, which in turn reduces the expected energy consumption while ensuring that the parametric yield of the cells remains above some prespecified threshold. To do this efficiently, an analytical method for estimating the yield of SRAM cells under process variations is also presented and integrated in the refinement procedure. A dual-gate controlled 6T SRAM cell operating at 324mV (in the near-threshold supply regime) is finally presented as a high-yield and energy-efficient memory cell in the 7nm FinFET technology.

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“…In 45nm technology, FinFET based designs offer better control over SCEs, low power, low leakage and better yield [8] which help to overcome the challenges in scaling. Thinner gate oxide assists in improvement of the short-channel effects (SCEs) [9].…”

Section: Introductionmentioning

confidence: 99%

Analysis of Conventional CMOS and FinFET based 6-T XOR-XNOR Circuit at 45nm Technology

Yadav¹,

Khandelwal²,

Akashe³

2013

IJCA

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As technology has scaled down, the implications of leakage current and power analysis for memory design have increased. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits due to the self-alignment of the two gates. Design for XOR and XNOR circuits is suggested to improve the speed and power. These circuits act as basic building blocks for many arithmetic circuits. This paper contrasts and evaluates the performance of conventional CMOS and FinFET based XOR-XNOR circuit design. It is based on the study of high speed, low power, and small area in XOR-XNOR digital circuits. The proposed FinFET based XOR and XNOR circuits have been designed using Cadence VIRTUOSO Tool applying voltage supply of 0.2 to 1.2 voltages, with temperature at 27 0 C and all the simulation results have been generated by Cadence SPECTRE simulator at 45nm technology. Simulation results exhibit low power, delay, power, delay product (PDP), and average dynamic power consumption.

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Asymmetrically Doped FinFETs for Low-Power Robust SRAMs

Cited by 59 publications

References 23 publications

Low Power Robust FinFET-Based SRAM Design in Scaled Technologies

Low Power Robust FinFET-Based SRAM Design in Scaled Technologies

A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations

Analysis of Conventional CMOS and FinFET based 6-T XOR-XNOR Circuit at 45nm Technology

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