Assessing the manufacturing tolerances and uniformity of CMOS compatible metamaterial fabrication

Abstract

The manufacturing tolerances of a stencil-lithography variant, membrane projection lithography, were investigated. In the first part of this work, electron beam lithography was used to create stencils with a range of linewidths. These patterns were transferred into the stencil membrane and used to pattern metallic lines on vertical silicon faces. Only the largest lines, with a nominal width of 84 nm, were resolved, resulting in 45 ± 10 nm (average ± standard deviation) as deposited with 135-nm spacing. Although written in the e-beam write software file as 84-nm in width, the lines exhibited linewidth bias. This can largely be attributed to nonvertical sidewalls inherent to dry etching techniques that cause proportionally larger impact with decreasing feature size. The line edge roughness can be significantly attributed to the grain structure of the aluminum nitride stencil membrane. In the second part of this work, the spatial uniformity of optically defined (as opposed to e-beam written) metamaterial structures over large areas was assessed. A Fourier transform infrared spectrometer microscope was used to collect the reflection spectra of samples with optically defined vertical split ring from 25 spatially resolved 300 × 300 μm regions in a 1-cm2 area. The technique is shown to provide a qualitative measure of the uniformity of the inclusions.

An asymmetric grating refractive index sensor generating quasi-bound states in the continuum with high figure of merit and temperature self-compensation

“…Since the FWHM of this structure was strongly influenced by the grating width, a discussion of the effect of fabrication tolerances was mandatory. Since the fabrication tolerances of the EBL mentioned above were about ±10 nm [41], we simulated the variation of the FWHM when the fabrication tolerances of ±10 nm were applied to the grating width. We considered the 20 cells as one period, as shown in figure 11.…”

Channel Length-Based Comparative Analysis of Temperature and Electrical Characteristics for SiNWT and GeNWT

“…The concept of nanotechnology involves the use of low dimensional materials with different structural configurations which include the nanowires, nano-rods, nanotubes or nanocrystalline films [20]. A nanowire in electronics engineering is a circular or rectangular cross-sectional nanostructure that has a thickness or diameter constrained to tens of nanometers or less and an unconstrained length.…”

Temperature Characteristics of Silicon Nanowire Transistor Depending on Oxide Thickness

“…Hani Taha AlAriqi 1 , Waheb A. Jabbar 1,2 , Yasir Hashim 3 , Hadi Bin Серед різних методів зондування та моніторингу датчики на основі на польових транзисторів (FET), привернули значну увагу як з боку промисловості, так і з академічних кіл. Завдяки своїм унікальним характеристикам, таким як невеликі розміри, легка вага, низька вартість, гнучкість, швидка реакція, стабільність і можливість подальшого зменшення масштабу, кремнієвий нанопровідний транзистор (SiNW-FET) може служити ідеальним наносенсором.…”

“…Design and fabrication of conventional metal oxide semiconductor field effect transistor (MOSFET) beyond sub-10 nm channel length become challenging issues due to short channel effects, such as leakage current, electrostatic limits, source-to-drain tunneling are very difficult, which causes a critical problem in terms of circuit reliability especially in complementary metal-oxide-silicon (CMOS). To overcome this issue, new 3D structures of transistors, including silicon nanowire transistors (SiNWT), were developed [1,2]. That incredible reaching has changed the world of nanotechnology.…”