2016
DOI: 10.1117/12.2210838
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Assessing the influence of the vertical epitaxial layer design on the lateral beam quality of high-power broad area diode lasers

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Cited by 10 publications
(4 citation statements)
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“…For broad area high power laser diode, the lateral far-field increase as the operation current increase. the optical mode is not only affected the etched index guided waveguide, but also affected by several other phenomena, such as thermal lensing induced by self-heating, lateral carrier accumulation at the stripe edges, lateral spatial hole burning, filamentation, and so on [5][6][7][8][9] . the optical mode and gain / loss distribution along lateral direction is modulated, higher order mode power lasing or the power percentage of high order mode increase, and lead to the lateral farfield booming.…”
Section: Introductionmentioning
confidence: 99%
“…For broad area high power laser diode, the lateral far-field increase as the operation current increase. the optical mode is not only affected the etched index guided waveguide, but also affected by several other phenomena, such as thermal lensing induced by self-heating, lateral carrier accumulation at the stripe edges, lateral spatial hole burning, filamentation, and so on [5][6][7][8][9] . the optical mode and gain / loss distribution along lateral direction is modulated, higher order mode power lasing or the power percentage of high order mode increase, and lead to the lateral farfield booming.…”
Section: Introductionmentioning
confidence: 99%
“…According to the waveguide theory, light will be confined to the high refractive index region. As a result, a filamentary structure is formed in BALs, which causes the optical field to develop into multiple lobes in the near and far fields [36]. Figure 1 shows the far-field image of a BAL, where several filaments with different intensities can be seen in the picture.…”
Section: Filamentation In Balsmentioning
confidence: 99%
“…This behaviour is presented here for an exemplary EDAS diode design with G = 0.26% in figure 1(b), where the CW power-voltage-current (PUI) characteristics at 25 °C and 75 °C heatsink temperature are shown. This vertical structure is used here throughout as a baseline and is taken from [11].…”
Section: Chip Design and The Challenge For Improvementmentioning
confidence: 99%