Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline

Abstract

Many crossbenchmarking results reported in the open literature raise optimistic expectations on the use of optical networks-on-chip (ONoCs) for high-performance and low-power on-chip communication. However, most of those previous works ultimately fail to make a compelling case for chip-level nanophotonic NoCs, especially for the lack of aggressive electronic baselines (ENoC), and the poor accuracy in physical- and architecture-layer analysis of the ONoC. This paper aims at providing the guidelines and minimum requirements so that nanophotonic emerging technology may become of practical relevance. The key differentiating factor of this work consists of contrasting ONoC solutions with an aggressive ENoC architecture with realistic complexity, performance, and power figures, synthesized on an industrial 40nm low-power technology. At the same time, key physical design issues and network interface architecture requirements for the ONoC under test are carefully assessed, thus paving the way for a well-grounded definition of the requirements for the emerging ONoC technology to achieve the energy break-even point with respect to pure electronic interconnect solutions in future multi- and many-core systems

Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization

“…We assume an 8mmx8mm die size and consider the optical parameters from [28]. We compute the maximum insertion loss of the optical network and calculate the minimum power required to reliably detect the optical message at the destination side.…”

“…The physical design of the optical ring is manually generated, while the λ-router is automatically generated [29]. The gwor is left out of the comparison due to the complexity of its physical design and the clear supremacy of the ring over filtered-based topologies [28]. We assume that the laser stabilization time is included in the partition set-up time, along with the execution time of the greedy algorithm.…”

The fast evolving landscape of on-chip communication

“…The need to come up with compelling cases for silicon nanophotonic technology has motivated the quest for higher accuracy, for instance by considering communication workloads [83], or the network interface overhead [84]. As the level of detail in comparative analysis between electrical and optical fabrics increases, it is becoming evident that while the optical interconnect fabric is not more energy efficient per se [86], the opticallyaugmented system is, since it can burn power for a lower amount of time due to the lower execution times that optical links enable [85].…”

“…In this respect, the experience of researchers starts to put together a few basic rules for trustworthy crossbenchmarking between NoCs on top of emerging technologies vs. their electrical counterparts. Next, such rules are reported by deriving them from the converging conclusions of [88] and [86]. They are tailored to optical interconnection networks, although the inspiring principles behind them could easily drive WiNoC research as well in the future:…”