ARTNoCs: An Evaluation Framework for Hardware Architectures of Real-Time NoCs

Hesham, Salma; Göhringer, Diana; Ghany, Mohamed A. Abd El

doi:10.1109/ipdpsw.2016.87

Cited by 6 publications

(5 citation statements)

References 8 publications

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“…Each compute tile features a private address space which allows the communication between all PEs and shared tile peripherals through shared data memory via an AXI interconnect. For inter-tile communication, a synchronous scalable NoC architecture ARTNoC [29] is used with a message-based communication model to manage data transfer between compute tiles. Furthermore, the proposed architecture is run-time adaptable which provides the flexibility to change types and number of active compute tiles during run-time.…”

Section: Background and Related Workmentioning

confidence: 99%

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AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors

Kamaleldin¹,

Göhringer²

2022

IEEE Access

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Tile-based many-core architectures are extensively used in modern system-on-chip designs to achieve scalable computing performance with adequate energy efficiency. Heterogeneity is the key element to boost computing performance and keep energy consumption under certain limits for several application domains. However, the steady increase of using many custom heterogeneous tiles leads to an expansion in design and integration cost with limited tiles re-usability. The recent widespread of opensource RISC-V ISA provides the potential to develop modular compute units that can be used for many application domains with high reduction in non-recurring engineering costs. The motivation of this work is to bring design modularity and adaptability features for heterogeneous tile-based many-core architectures by increasing their flexibility to realize different many-core configurations with less design time and costs. In this work, AGILER is proposed as an adaptive tile-base many-core architecture for heterogeneous RISC-V based processors. The proposed architecture consists of modular and adaptable heterogeneous multi-/single-core compute tiles that supports 32-/64-bit RISC-V ISAs with different memory hierarchies. Intertile communication is developed based on a scalable network-on-chip architecture to achieve a high degree of system scalability. AGILER supports run-time adaptation through a custom internal reconfiguration manager for dynamic and partial reconfiguration over Xilinx FPGAs. Evaluation results demonstrate that the proposed architecture features a scalable computing performance up to 685 MOPS for 8x32-bit tiles and 316 MOPS for 8x64-bit tiles with a scalable memory bandwidth up to 7.4 GB/s. AGILER is evaluated on Xilinx Virtex Ultrascale+ FPGA with a maximum reconfiguration time of 38.1 ms for a single compute tile.INDEX TERMS Many-core architecture, parallel computing, RISC-V, network-on-chip (NoC), field programmable gate array (FPGA), reconfigurable computing.

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Section: Background and Related Workmentioning

confidence: 99%

“…In this work, the real-time NoC architecture ARTNoC [29] is used for inter-tile communication and to provide the required high scalability for the proposed many-core architecture. The used NoC provides guaranteed quality of service (QoS) in terms of bandwidth and end-to-end latency.…”

Section: Scalability and Communication Modelmentioning

confidence: 99%

AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors

Kamaleldin¹,

Göhringer²

2022

IEEE Access

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“…Hence, the proposed many-core is implemented as a cluster-based architecture. The clusters are connected through a synchronous NoC architecture ARTNoC [23] using stream network interfaces. Each cluster tightly couple multiple RISC-V PEs with shared instruction/data memories using a shared AXI interconnect.…”

Section: Tablementioning

confidence: 99%

“…A Network-on-Chip (NoC) is used on large scale Multi-Processor System-on-Chip (MPSoC) or many-core architectures to connect dozens to hundreds of PEs or processing clusters together, providing on-chip end-to-end communication paradigm and increasing the system scalability. In this work, the ARTNoC [23] real-time NoC architecture is used for inter-cluster communication in the proposed many-core architecture. The NoC provides guaranteed quality of service (QoS) in terms of bandwidth and end-toend latency.…”

Section: Network-on-chipmentioning

confidence: 99%

Towards a Modular RISC-V Based Many-Core Architecture for FPGA Accelerators

2020

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Multi-/Many-core architectures are emerging as scalable, high-performance and energy-efficient computing platforms suitable for a variety of application domains from edge to cloud computing. Recently, the appearance of RISC-V open-source ISA creates new possibilities to develop customized computing platforms with high savings in the non-recurring engineering costs. Moreover, the current trends toward open-source hardware frameworks are aimed to reduce design time and cost for complex system-on-chip architectures. Therefore, modularity and re-usability of hardware components are major challenges for flexible hardware architectures. The motivation behind this work is to introduce a modular cluster-based many-core architecture for FPGA accelerators that is re-usable and flexible tailored to implement different many-core taxonomies with less design time and costs by using regular and replicated sets of computing, memory, and interconnection blocks. The proposed many-core architecture is built using multiple processing clusters coupled with a NoC for communication which allows a high degree of design scalability. The processing cluster inside features a configurable multi-core architecture consisting of multiple RISC-V processing elements (PE) tightly coupled with a bus-based interconnection for intra-cluster communication using parameterized scratchpad shared memory. Each PE features a single RISC-V core with a tightly coupled parameterized scratchpad local memory and generic AXI interface. Evaluation results demonstrate that the proposed architecture features a scalable computing performance of 501 MOp/s for 4 clusters and 878 MOp/s for 8 clusters. Moreover, a scalable memory bandwidth up to 4.3 GB/s is achieved for 9 clusters with a power consumption of 1.4 W per cluster utilizing 7.7% of on-chip memory resources. The many-core architecture is implemented and evaluated on Xilinx Virtex Ultrascale+ with the feature of changing the architecture configurations during run-time using dynamic and partial reconfiguration which provides more flexibility and re-usability.INDEX TERMS Many-core architecture, parallel computing, RISC-V, network-on-chip (NoC), field programmable gate array (FPGA), reconfigurable computing.

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“…At the network layer, several design decisions with regards to the routing algorithm and router design can be made [61], [62]. For example, Hesham et al suggested that packet switching is more energy-efficient for streaming applications compared to circuit-switching routing scheme whereas for discrete packets circuit-switching performs better [63], [64]. Other researchers suggested that an optimum energy-efficient architecture could be a heterogeneous one, i.e.…”

Section: B Power-efficient Hardware For Mixed Criticality Systemsmentioning

confidence: 99%

SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems

Fakih

Lenz

Azkarate-Askasua

et al. 2017

Microprocessors and Microsystems

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With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER 1 targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality real-time systems (MCRTES). This article will introduce the requirements that a power efficient SoC has to meet and the challenges such a SoC has to overcome.

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ARTNoCs: An Evaluation Framework for Hardware Architectures of Real-Time NoCs

Cited by 6 publications

References 8 publications

AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors

AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors

Towards a Modular RISC-V Based Many-Core Architecture for FPGA Accelerators

SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems

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