Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies

Vandebon, Jessica; Coutinho, J.G.F.; Luk, Wayne; Nurvitadhi, Eriko; Todman, Tim

doi:10.1109/fccm48280.2020.00032

Cited by 8 publications

(8 citation statements)

References 7 publications

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“…This paper extends our work in [1], introducing more complex analysis and optimisation strategies, such as polyhedral analysis, pattern-matching for non-trivial transformations such as line-buffering, and multi-kernel execution models with channels for direct kernel-to-kernel communication. In addition, we cover additional benchmarks from the Rosetta HLS (High-Level Synthesis) benchmark suite [2], namely: digit recognition, 3D-rendering, and optical flow.…”

Section: Introductionmentioning

confidence: 76%

“…Table 4 includes speedups achieved compared to the baseline, unoptimised input software. We also include speedups achieved by designs automatically optimised using Artisan with OpenMP to target multiple CPU threads, following the strategy presented in [1]. For 3D-rendering and optical flow loops are not parallelisable, so there is no applicable OpenMP optimisation.…”

Section: Performance Resultsmentioning

confidence: 99%

“…In this section, we present the main mechanisms implemented in Artisan which allow meta-program developers to traverse and manipulate application source-code: query and instrument. For more implementation details, including how an AST is modelled from input code and how code is versioned, refer to our previous work [1].…”

Section: Source-code Analysis and Manipulationmentioning

confidence: 99%

“…We apply meta-programs to six benchmark applications: AdPredictor, K-Means Classification, N-Body Simulation, Digit Recognition, 3D-Rendering, and Optical Flow. The first three benchmarks are extended from our work in [1], and the latter three are from the Rosetta HLS benchmark suite [2]. These benchmarks cover domains including machine learning, physics and image processing.…”

Section: [Y-1+i][x-1+j]mentioning

confidence: 99%

See 3 more Smart Citations

Enhancing High-Level Synthesis Using a Meta-Programming Approach

Vandebon

Coutinho²,

Luk

et al. 2021

IEEE Trans. Comput.

Self Cite

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In today's increasingly heterogeneous compute landscape, there is high demand for design tools that offer seemingly contradictory features: portable programming abstractions that hide underlying architectural detail, and the capability to optimise and exploit architectural features. Our meta-programming approach, Artisan, decouples application functionality from optimisation concerns to address the complexity of mapping high-level application descriptions onto heterogeneous platforms from which they are abstracted. With Artisan, application experts focus on algorithmic behaviour, while platform and domain experts focus on optimisation and mapping. Artisan offers complete design-flow orchestration in a unified programming environment based on Python 3 to enable accessible codification of reusable optimisation strategies that can be automatically applied to high-level application descriptions. We have developed and evaluated an Artisan prototype and a set of customised meta-programs used to automatically optimise six case study applications for CPU+FPGA targets. In our experiments, Artisan-optimised designs achieve the same order of magnitude speedup as manually optimised designs compared to corresponding unoptimised software.

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Section: Introductionmentioning

confidence: 76%

Section: Performance Resultsmentioning

confidence: 99%

Section: Source-code Analysis and Manipulationmentioning

confidence: 99%

Section: [Y-1+i][x-1+j]mentioning

confidence: 99%

See 2 more Smart Citations

Enhancing High-Level Synthesis Using a Meta-Programming Approach

Vandebon

Coutinho²,

Luk

et al. 2021

IEEE Trans. Comput.

Self Cite

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show abstract

“…The Design Space Generator, depicted in Figure 1, adapts the Rose Compiler [1] to analyze the kernel AST and extract the required information for running the DSE such as the loops in the design, their trip-count, and available bit-width. Artisan [47] employs a similar approach for analyzing the code. However, it only considers unroll pragma in code instrumentation.…”

Section: Design Space Partitioningmentioning

confidence: 99%

AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators

Sohrabizadeh

Gao³

et al. 2022

ACM Trans. Des. Autom. Electron. Syst.

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Adopting FPGA as an accelerator in datacenters is becoming mainstream for customized computing, but the fact that FPGAs are hard to program creates a steep learning curve for software programmers. Even with the help of high-level synthesis (HLS) , accelerator designers still have to manually perform code reconstruction and cumbersome parameter tuning to achieve optimal performance. While many learning models have been leveraged by existing work to automate the design of efficient accelerators, the unpredictability of modern HLS tools becomes a major obstacle for them to maintain high accuracy. To address this problem, we propose an automated DSE framework— AutoDSE —that leverages a bottleneck-guided coordinate optimizer to systematically find a better design point. AutoDSE detects the bottleneck of the design in each step and focuses on high-impact parameters to overcome it. The experimental results show that AutoDSE is able to identify the design point that achieves, on the geometric mean, 19.9× speedup over one CPU core for MachSuite and Rodinia benchmarks. Compared to the manually optimized HLS vision kernels in Xilinx Vitis libraries, AutoDSE can reduce their optimization pragmas by 26.38× while achieving similar performance. With less than one optimization pragma per design on average, we are making progress towards democratizing customizable computing by enabling software programmers to design efficient FPGA accelerators.

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HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming

Ejjeh

Medvinsky

Councilman

et al. 2022

2022 IEEE 33rd International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

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Current FPGA programming tools require extensive hardware-specific manual code tuning to achieve performance, which is intractable for most software application teams. We present HPVM2FPGA, a novel end-to-end compiler and autotuning system that can automatically tune hardware-agnostic programs for FPGAs. HPVM2FPGA uses a hardware-agnostic abstraction of parallelism as an intermediate representation (IR) to represent hardware-agnostic programs. HPVM2FPGA's powerful optimization framework uses sophisticated compiler optimizations and design space exploration (DSE) to automatically tune a hardware-agnostic program for a given FPGA. HPVM2FPGA is able to support software programmers by shifting the burden of performing hardware-specific optimizations to the compiler and DSE. We show that HPVM2FPGA can achieve up to 33× speedup compared to unoptimized baselines and can match the performance of hand-tuned HLS code for three of four benchmarks. We have designed HPVM2FPGA to be a modular and extensible framework, and we expect it to match handtuned code for most programs as the system matures with more optimizations. Overall, we believe that it constitutes a solid step closer to fully hardware-agnostic FPGA programming, making it a suitable cornerstone for future FPGA compiler research.

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Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies

Cited by 8 publications

References 7 publications

Enhancing High-Level Synthesis Using a Meta-Programming Approach

Enhancing High-Level Synthesis Using a Meta-Programming Approach

AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators

HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming

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