AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators

Abstract

Adopting FPGA as an accelerator in datacenters is becoming mainstream for customized computing, but the fact that FPGAs are hard to program creates a steep learning curve for software programmers. Even with the help of high-level synthesis (HLS) , accelerator designers still have to manually perform code reconstruction and cumbersome parameter tuning to achieve optimal performance. While many learning models have been leveraged by existing work to automate the design of efficient accelerators, the unpredictability of modern HLS tools becomes a major obstacle for them to maintain high accuracy. To address this problem, we propose an automated DSE framework— AutoDSE —that leverages a bottleneck-guided coordinate optimizer to systematically find a better design point. AutoDSE detects the bottleneck of the design in each step and focuses on high-impact parameters to overcome it. The experimental results show that AutoDSE is able to identify the design point that achieves, on the geometric mean, 19.9× speedup over one CPU core for MachSuite and Rodinia benchmarks. Compared to the manually optimized HLS vision kernels in Xilinx Vitis libraries, AutoDSE can reduce their optimization pragmas by 26.38× while achieving similar performance. With less than one optimization pragma per design on average, we are making progress towards democratizing customizable computing by enabling software programmers to design efficient FPGA accelerators.

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

“…In addition to this classification, a third group appears including DSE synthesis-based and supervised learning. According to [15], HLS DSE can be developed using model-based and model-free techniques. Model-based techniques are composed of tools and methodologies that use analytical models, whereas model-free techniques include approaches where the HLS tool is treated as a black box.…”

“…According to Sohrabizadeh et al [15], HLS DSE can be developed using model-based and model-free techniques. Model-based techniques comprise tools and methodologies that use analytical models.…”

“…• It is important to identify the strengths and weaknesses of a given design space explorer. This can be performed using benchmarks, as was made in [15], [115], [114], [132], and [77], among others. • Mapping an optimal design from the DSE to the FPGA/SoC can be challenging while maintaining the QoR reported by the DSE engine, mainly latency.…”

A Modified KNN Algorithm for High-Performance Computing on FPGA of Real-Time m-QAM Demodulators

“…Although these tools allow accelerating the design flow, there are still aspects related to the use of optimization directives and design space evaluation that require considerable effort. In some cases, the need for a certain level of hardware expertise to reach an adequate level of optimization persists [22]. For this reason, some authors have focused on developing tools to simplify the use of optimization directives as in [22] or give guidelines to understand the operation and performance effects of some types of algorithms when using these directives as in [23].…”

“…In some cases, the need for a certain level of hardware expertise to reach an adequate level of optimization persists [22]. For this reason, some authors have focused on developing tools to simplify the use of optimization directives as in [22] or give guidelines to understand the operation and performance effects of some types of algorithms when using these directives as in [23]. There are several FPGA real-time implementations of the KNN algorithm in the literature.…”