Area Efficient Implementation of FIR Filter Using Distributed Arithmetic with Offset Binary Coding

Kalaiyarasi, D.; Reddy, T. Kalpalatha

doi:10.9790/4200-04330109

Cited by 5 publications

(2 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Kalaiyarasi and Kalpalatha Reddy [8] proposed an efficient realization of Distributed Athematic with Offset Binary Coding for the implementation of the FIR filter. The size of the LUT increases with the coefficient values.…”

Section: Related Workmentioning

confidence: 99%

Implementation of Efficient FIR Filter Architectures using Distributed Arithmetic Computation for Digital Channelizer of SDR

Bhadavath

Livinsa

2022

Preprint

View full text Add to dashboard Cite

Always an efficient and low complexity reconfigurable filter architecture is required for the channel filters of digital channelizer in Software Defined Radio (SDR). In this paper, a block-based reconfigurable FIR filter is proposed using Distributed Arithmetic (DA) Technique. The complexity of the conventional multiplier is replaced with the DA multiplication process and the throughput of the entire filter is increased by block processing. Memory reuse is also achieved in the proposed direct form systolic FIR filter architecture due to parallel processing. The different bandwidth filters and the corresponding coefficients are stored in the LUTs concerning different channels of the digital channelizer. The proper channel selection is used to choose an appropriate filter and partial products are generated using Offset Binary Coding (OBC). Next, the multiplication process is done by the proposed decomposed LUT-based DA technique in the processing blocks of the filter. The proposed filter is coded by Verilog and synthesized by ASIC-based tools from Cadence in 45 nm CMOS technology. The performance parameters such as area, delay, power consumption, ADP, and PDP are evaluated and compared with the state-of-the-art works. The ADP and PDP values are saved by 44.1% and 30% by the proposed OBC-DA-based filter architecture than the conventional DA-based filter architecture, respectively.

show abstract

Section: Related Workmentioning

confidence: 99%

Implementation of Efficient FIR Filter Architectures using Distributed Arithmetic Computation for Digital Channelizer of SDR

Bhadavath

Livinsa

2022

Preprint

View full text Add to dashboard Cite

show abstract

“…Simulation results show that the fabricated chip operates up to 86 MHz and consumes 16.5 mW power from a 2.5 V power supply. Kalaiyarasi and Kalpalatha Reddy 8 proposed an efficient realization of DA with OBC for the implementation of the FIR filter. The proposed OBC‐based DA algorithm reduces the LUT size and delay.…”

Section: Introductionmentioning

confidence: 99%

Very large scale integration implementation of efficient finite impulse response filter architectures using novel distributed arithmetic for digital channelizer of software defined radio

Bhadavath

Livinsa

2022

Circuit Theory & Apps

View full text Add to dashboard Cite

Always an efficient and low complexity reconfigurable filter architecture is required for the channel filters of digital channelizer in software-defined radio (SDR). In this paper, a block-based reconfigurable finite impulse response (FIR) filter is proposed using distributed arithmetic (DA) technique. The complexity of the conventional multiplier is replaced with the DA multiplication process, and the throughput of the entire filter is increased by block processing. Memory reuse is also achieved in the proposed direct form systolic FIR filter architecture due to parallel processing. The different bandwidth filters and the corresponding coefficients are stored in the look-up tables (LUTs) concerning different channels of the digital channelizer. The proper channel selection is used to choose an appropriate filter and partial products are generated using offset binary coding (OBC). Next, the multiplication process is done by the proposed decomposed LUT-based DA technique in the processing blocks of the filter. The proposed filter is coded by Verilog and synthesized by application specific integrated circuit (ASIC)-based tools from Cadence in 45 nm CMOS technology. The performance parameters such as area, delay, power consumption, area-delay product (ADP), and power delay product (PDP) are evaluated and compared with state-of-the-art works. The ADP and PDP values are saved by 44.1% and 30% by the proposed OBC-DA-based filter architecture than the conventional DA-based filter architecture, respectively.

show abstract

Design and implementation of Least Mean Square adaptive FIR filter using offset binary coding based Distributed Arithmetic

Kalaiyarasi

Reddy

2019

Microprocessors and Microsystems

View full text Add to dashboard Cite

Area Efficient Implementation of FIR Filter Using Distributed Arithmetic with Offset Binary Coding

Cited by 5 publications

References 6 publications

Implementation of Efficient FIR Filter Architectures using Distributed Arithmetic Computation for Digital Channelizer of SDR

Implementation of Efficient FIR Filter Architectures using Distributed Arithmetic Computation for Digital Channelizer of SDR

Very large scale integration implementation of efficient finite impulse response filter architectures using novel distributed arithmetic for digital channelizer of software defined radio

Design and implementation of Least Mean Square adaptive FIR filter using offset binary coding based Distributed Arithmetic

Contact Info

Product

Resources

About