Design and implementation of Least Mean Square adaptive FIR filter using offset binary coding based Distributed Arithmetic

Kalaiyarasi, D.; Reddy, T. Kalpalatha

doi:10.1016/j.micpro.2019.102884

Cited by 9 publications

(2 citation statements)

References 14 publications

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“…It specifically targets the sum of products computation, predominately featuring in many important digital signal processing (DSP) filtering and frequency transformation functions. It can be used to implement a wide variety of applications, such as signal processing (Lu, Duan, Halak, & Kazmierski, 2019), filters (Kalaiyarasi & Reddy, 2019;Kumar, Shrivastava, Tiwari, & Mishra, 2019), control systems (Chan, Moallem, & Wang, 2004, 2007, system-on-chip (SoC) applications (Khawam, Arslan, & Westall, 2004) and discrete cosine transforms (Pan, Shams, & Bayoumi, 1999;Sowmya & Mathew, 2019;Yu & Swartzlander Jr., 2001). All these implementations utilise lookup tables to store certain aspects of the computation.…”

Section: Lookup Table Reconfigurationmentioning

confidence: 99%

Improving functional density of time-critical applications using hardware-based dynamic reconfiguration and bitstream specialisation

Roux

Schoor

Vuuren

2019

SACJ

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The dynamic reconfiguration of an FPGA has many advantages, but the overhead from the process reduces the functional density of applications. Functional density is an indication of the composite benefits a reconfigured application obtains above its generic counterpart and measures the computational throughput per unit hardware resources. Typically, only quasi-static applications obtain a functional density advantage by dynamically reconfiguring its parameters. Contributing to the functional density reduction of applications with tight time constraints is the overhead to generate a new configuration, and the time it takes to load it onto the device. Normally these applications have to reuse their hardware numerous times between configurations before obtaining a functional density advantage. The most promising reconfiguration method to improve functional density with minimal hardware reuse was one that extracts certain characteristics from the bitstream and then implements a bitstream specialiser that generates new hardware at bit-level while the device is being reconfigured. While it was shown that this method allows reconfiguration of an application in real-time, its effect on functional density was not determined. This paper will show that a significant increase in functional density can be achieved for applications where reconfiguration is required before the next execution cycle of the application.

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Section: Lookup Table Reconfigurationmentioning

confidence: 99%

Improving functional density of time-critical applications using hardware-based dynamic reconfiguration and bitstream specialisation

Roux

Schoor

Vuuren

2019

SACJ

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“…There were 40% less LUT flip flop pairs used, at the expense of speed. A DA-based LMS adaptive filter using offset binary coding without LUT has been presented, in order to improve the performance of bit-serial operation [36]. Additionally, a DA-RNS-based filter implementation has been used for the effective calculation of modular inner products in a FIR filter [28].…”

Section: Introductionmentioning

confidence: 99%

Improving Generalized Discrete Fourier Transform (GDFT) Filter Banks with Low-Complexity and Reconfigurable Hybrid Algorithm

Otunniyi

Myburgh

2020

Digital

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With ever-increasing wireless network demands, low-complexity reconfigurable filter design is expected to continue to require research attention. Extracting and reconfiguring channels of choice from multi-standard receivers using a generalized discrete Fourier transform filter bank (GDFT-FB) is computationally intensive. In this work, a lower compexity algorithm is written for this transform. The design employs two different approaches: hybridization of the generalized discrete Fourier transform filter bank with frequency response masking and coefficient decimation method 1; and the improvement and implementation of the hybrid generalized discrete Fourier transform using a parallel distributed arithmetic-based residual number system (PDA-RNS) filter. The design is evaluated using MATLAB 2020a. Synthesis of area, resource utilization, delay, and power consumption was done on a Quartus 11 Altera 90 using the very high-speed integrated circuits (VHSIC) hardware description language. During MATLAB simulations, the proposed HGDFT algorithm attained a 66% reduction, in terms of number of multipliers, compared with existing algorithms. From co-simulation on the Quartus 11 Altera 90, optimization of the filter with PDA-RNS resulted in a 77% reduction in the number of occupied lookup table (LUT) slices, an 83% reduction in power consumption, and an 11% reduction in execution time, when compared with existing methods.

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Compressed Coding Method for Information Transmission via UAVs Over Remote Ocean Environments

Jiang,

Pan,

Sun

2024

Lecture Notes in Electrical Engineering

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Design and implementation of Least Mean Square adaptive FIR filter using offset binary coding based Distributed Arithmetic

Cited by 9 publications

References 14 publications

Improving functional density of time-critical applications using hardware-based dynamic reconfiguration and bitstream specialisation

Improving functional density of time-critical applications using hardware-based dynamic reconfiguration and bitstream specialisation

Improving Generalized Discrete Fourier Transform (GDFT) Filter Banks with Low-Complexity and Reconfigurable Hybrid Algorithm

Compressed Coding Method for Information Transmission via UAVs Over Remote Ocean Environments

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