Wireless sensor networks (WSNs) are widely used in many environments and adverse terrains. Location estimation of sensor nodes is still a crucial area of research because of new localization requirements. One of the main hurdles facing sensor localization in WSNs is accuracy. Many localization algorithms and techniques have been proposed to estimate the position of nodes. In this paper, we consider an RSSI (received signal strength indicator) range based localization algorithm that relies on measuring the received signal strength indicator for distance estimation. In this work, we conducted the experiments in outdoor and indoor environments to derive the path loss model. The result shows that the outdoor environment has the better distance estimation than an indoor environment. Hence we investigate the effect of varying the anchor node density on localization error with minimum number of anchor nodes thereby enhancing an accuracy of the network.
Recent developments in radio technology and processing systems, Wireless Sensor Networks (WSNs) are tremendously being used to perform an assortment of tasks from their atmosphere. Localization plays the most important task in WSNs. Accuracy is the one of the major problems facing localization. In this paper, we propose an improved localization algorithm based on the learning concept of support vector machine (SVM). In SVM classification the finite size of grid cells offer the localization accuracy. The localization error using the proposed algorithm is calculated and compared with basic SVM and fuzzy logic. Simulation result demonstrates that the improved support vector machine can effectively reduce the localization error and thus achieve the objective of better accuracy.
Always an efficient and low complexity reconfigurable filter architecture is required for the channel filters of digital channelizer in software-defined radio (SDR). In this paper, a block-based reconfigurable finite impulse response (FIR) filter is proposed using distributed arithmetic (DA) technique. The complexity of the conventional multiplier is replaced with the DA multiplication process, and the throughput of the entire filter is increased by block processing. Memory reuse is also achieved in the proposed direct form systolic FIR filter architecture due to parallel processing. The different bandwidth filters and the corresponding coefficients are stored in the look-up tables (LUTs) concerning different channels of the digital channelizer. The proper channel selection is used to choose an appropriate filter and partial products are generated using offset binary coding (OBC). Next, the multiplication process is done by the proposed decomposed LUT-based DA technique in the processing blocks of the filter. The proposed filter is coded by Verilog and synthesized by application specific integrated circuit (ASIC)-based tools from Cadence in 45 nm CMOS technology. The performance parameters such as area, delay, power consumption, area-delay product (ADP), and power delay product (PDP) are evaluated and compared with state-of-the-art works. The ADP and PDP values are saved by 44.1% and 30% by the proposed OBC-DA-based filter architecture than the conventional DA-based filter architecture, respectively.
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