Architecture, design and technology guidelines for crosspoint memories

Abstract

While standalone Flash memories (NAND) are facing their physical limitations, the emergence of resistive switching memories (RRAM) is seen as a solution for high density, low cost and low energy NAND replacement candidate. However, it has been shown that deeply scaled, high density RRAM architectures, such as crosspoint, suffer of voltage drop effects (IR drop) in metal lines, periphery overhead and metal line charging time due to injected current during programming operations and sneaking currents through unselected bitcells. In this work, we first propose several innovative models for IRdrop, periphery overhead and array-line charging time accounting for in-array multiple bit-write operation. Then, we introduce a new methodology for crosspoint memory design to determine IRdrop, periphery overhead and timing associated with the optimal characteristics of 1 selector-1 resistance (1S1R) device. We apply the proposed methodology to various half metal pitch memory technology nodes (from 50nm to 15nm) and to several written word sizes (from 1 to 32 bits). We show that for 1 bit programmed per array, the RRAM programming current has to be lower than 30µA and the selector leakage current lower than 10nA and that limitations increase as soon as multiple bits are written simultaneously in the same array. This, suggests massively parallel multi-bank write of a small number of bits per array, as the best solution for the RRAM memories to be competitive with NAND memories

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

“…First, it seems mandatory to justify the choice of keeping on logic transistors as selectors for eNVM while most of the community rushes for studies with fully BEoL bitcells or unconventional Front End of Line (FEoL) selectors. Extremely high transistor-less bitcell density architectures such as crosspoint/crossbar or Vertical RRAM (VRRAM) have been proposed but, as we demonstrated in [33], due to the high voltages required (3 to 6Volts), peripheral circuitry becomes area hungry and makes it not suitable for embedded memory replacement. On the other hand, extremely aggressive FEoL process, as used in [34], cannot be co-integrated with logic gates, requiring extremely process steps and thus making it not suitable for embedded memories.…”

A Parasitic Resistance-Adapted Programming Scheme for Memristor Crossbar-Based Neuromorphic Computing Systems

“…In a memristor crossbar array, some amount of voltage drop can be caused by parasitic resistance, also known as wire resistance along the row and the column lines [19,[24][25][26][27][28]. Hereinafter "wire resistance" and "parasitic resistance" are used interchangeably.…”

“…The impact of wire resistance becomes inevitable when the array size increases [22]. To mitigate the impact of wire resistance, several interesting schemes were proposed [25][26][27][28]. A design methodology has been proposed to reduce the impact of wire resistance in a one-selector-one resistive device (1S1R) crossbar array [27].…”

“…To mitigate the impact of wire resistance, several interesting schemes were proposed [25][26][27][28]. A design methodology has been proposed to reduce the impact of wire resistance in a one-selector-one resistive device (1S1R) crossbar array [27]. The proposed design methodology seems to be complicated since the physical specification of the devices must be considered [27].…”

“…A design methodology has been proposed to reduce the impact of wire resistance in a one-selector-one resistive device (1S1R) crossbar array [27]. The proposed design methodology seems to be complicated since the physical specification of the devices must be considered [27]. Another approach to deal with the wire resistance is to use a dynamic reference scheme [25].…”