2019
DOI: 10.3390/ma12244097
|View full text |Cite
|
Sign up to set email alerts
|

A Parasitic Resistance-Adapted Programming Scheme for Memristor Crossbar-Based Neuromorphic Computing Systems

Abstract: Memristor crossbar arrays without selector devices, such as complementary-metal oxide semiconductor (CMOS) devices, are a potential for realizing neuromorphic computing systems. However, wire resistance of metal wires is one of the factors that degrade the performance of memristor crossbar circuits. In this work, we propose a wire resistance modeling method and a parasitic resistance-adapted programming scheme to reduce the impact of wire resistance in a memristor crossbar-based neuromorphic computing system. … Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

0
7
0

Year Published

2020
2020
2023
2023

Publication Types

Select...
4
1

Relationship

0
5

Authors

Journals

citations
Cited by 5 publications
(7 citation statements)
references
References 36 publications
0
7
0
Order By: Relevance
“…Truong proposes a method to correct the line resistances when writing the desired values of conductance in DNN for feedforward applications [19]. Circuit simulations of a 64 × 16 single layer perceptron for the recognition of 26 characters (8 × 8 grayscale pixels) support significant improvements of network recognition when line resistance increases above 1.5Ω.…”
Section: Synopsismentioning
confidence: 98%
“…Truong proposes a method to correct the line resistances when writing the desired values of conductance in DNN for feedforward applications [19]. Circuit simulations of a 64 × 16 single layer perceptron for the recognition of 26 characters (8 × 8 grayscale pixels) support significant improvements of network recognition when line resistance increases above 1.5Ω.…”
Section: Synopsismentioning
confidence: 98%
“…[ 285 ] Parasitic resistance mainly refers to wire resistance along the row and column lines in memristor crossbar arrays. [ 285 ] During the read operation, parasitic conductive paths in unselected cells will degrade the output signal and result in massive sneak path leakage which will further increase the possibility of misreading during data reading. During the write process, the voltage drop introduced by the parasitic resistance may cause insufficient write voltage of the selected cells, resulting in programming errors.…”
Section: Challenges In Device and System Levelsmentioning
confidence: 99%
“…An adaptive programming technique considering parasitic resistance correction was developed, to avoid to use the additional correction circuit or selecting devices. Figure 12(a) show a conventional programming method, where each memristive crossing-point is programmed to corresponding memristance value (Truong 2019). In figure 12(a), for the ith column, the jth input produces the column current, I j,i , represented by the dashed line.…”
Section: Correction Technique Of Parasitic Line Resistance In Memrist...mentioning
confidence: 99%
“…Figure 13 shows the comparison of recognition rate between the conventional programming method and the adaptive programming approach when the parasitic line resistance varies from 0.5 Ω to 3 Ω (Truong 2019).…”
Section: Correction Technique Of Parasitic Line Resistance In Memrist...mentioning
confidence: 99%