Architecture and compilation for data bandwidth improvement in configurable embedded processors

Cong, Jason; Han, Guoling; Zhang, Zhiru

doi:10.1109/iccad.2005.1560075

Cited by 14 publications

(16 citation statements)

References 11 publications

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“…Though the previous works [4,5,12] improve the data bandwidth, they do not address the related problems of encoding multiple operands in a fixed-length instruction format and data hazards.…”

Section: Related Workmentioning

confidence: 99%

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Exploiting forwarding to improve data bandwidth of instruction-set extensions

Jayaseelan

Liu

Mitra

2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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Application-specific instruction-set extensions (custom instructions) help embedded processors achieve higher performance. Most custom instructions offering significant performance benefit require multiple input operands. Unfortunately, RISC-style embedded processors are designed to support at most two input operands per instruction. This data bandwidth problem is due to the limited number of read ports in the register file per instruction as well as the fixed-length instruction encoding. We propose to overcome this restriction by exploiting the data forwarding feature present in processor pipelines. With minimal modifications to the pipeline and the instruction encoding along with cooperation from the compiler, we can supply up to two additional input operands per custom instruction. Experimental results indicate that our approach achieves 87-100% of the ideal performance limit for standard benchmark programs. Additionally, our scheme saves 25% energy on an average by avoiding unnecessary accesses to the register file.

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Section: Related Workmentioning

confidence: 99%

“…Cong et al [4,5] eliminate these explicit transfer of operands with the help of a shadow register file associated with the CFU. Shadow register file is similar to the internal register file of Nios-II in that they both provide input operands to the CFUs.…”

Section: Related Workmentioning

confidence: 99%

Exploiting forwarding to improve data bandwidth of instruction-set extensions

Jayaseelan

Liu

Mitra

2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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show abstract

“…While steady progress has been made in the tools and methodologies of automatic instruction set extension for configurable processors, recent study has shown that the limited data bandwidth available in the core processor (e.g., the number of simultaneous accesses to the register file) becomes a serious performance bottleneck. [10] proposes a new low-cost architectural extension and associated compilation techniques to address the data bandwidth problem. [10] also present a novel simultaneous global shadow register binding with a hash function generation algorithm to take full advantage of the extension.…”

Section: Related Workmentioning

confidence: 99%

“…[10] proposes a new low-cost architectural extension and associated compilation techniques to address the data bandwidth problem. [10] also present a novel simultaneous global shadow register binding with a hash function generation algorithm to take full advantage of the extension. The application of this approach leads to a nearly-optimal performance speedup (within 2% of the ideal speedup).…”

Section: Related Workmentioning

confidence: 99%

A Modern Parallel Register Sharing Architecture for Code Compilation

Kumar¹,

Singh²

2010

IJCA

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The design of many-core-on-a-chip has allowed renewed an intense interest in parallel computing. On implementation part, it has been seen that most of applications are not able to use enough parallelism in parallel register sharing architecture. The exploitation of potential performance of superscalar processors has shown that processor is fed with sufficient instruction bandwidth. The fetcher and the Instruction Stream Buffer (ISB) are the key elements to achieve this target. Beyond the basic blocks, the instruction stream is not supported by currents ISBs. The split line instruction problem depreciates this situation for x86 processors. With the implementation of Line Weighted Branch Target Buffer (LWBTB), the advance branch information and reassembling of cache lines can be predicted by the ISB. The ISB can fetch some more valid instructions in a cycle through reassembling of original line containing instructions for next basic block. If the cache line size is more than 64 bytes, then there exist good chances to have two basic blocks in the recognized instruction line.The code generation for parallel register share architecture involves some issues that are not present in sequential code compilation and is inherently complex. To resolve such issues, a consistency contract between the code and the machine can be defined and a compiler is required to preserve the contract during the transformation of code. In this paper, we present a correctness framework to ensure the protection of the contract and then we use code optimization for verification under parallel code.

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“…Cong, Han and Zhiru Zhang (2005) [5] represents a very low cost architectural extension and a compilation technique responsible for data bandwidth problem. A novel parallel global register binding is also presented in [5] with the help of hash function algorithm. This leads to a nearly optimal performance speedup of 2% of ideal speedup.…”

Section: Related Workmentioning

confidence: 99%

Role of Multiblocks in Control Flow Prediction using Parallel Register Sharing Architecture

Kumar¹,

Singh²

2010

IJCA

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In this paper we present control flow prediction (CFP) in parallel register sharing architecture to achieve high degree of ILP. The main idea behind this concept is to use a step beyond the prediction of common branch and permitting the architecture to have the information about the CFG (Control Flow Graph) components of the program to have better branch decision for ILP. The navigation bandwidth of prediction mechanism depends upon the degree of ILP. It can be increased by increasing control flow prediction at compile time. By this the size of initiation is increased that allows the overlapped execution of multiple independent flow of control. The multiple branch instruction can also be allowed. These are intermediate steps to be taken in order to increase the size of dynamic window to achieve a high degree of instruction level parallelism exploitation.

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Architecture and compilation for data bandwidth improvement in configurable embedded processors

Cited by 14 publications

References 11 publications

Exploiting forwarding to improve data bandwidth of instruction-set extensions

Exploiting forwarding to improve data bandwidth of instruction-set extensions

A Modern Parallel Register Sharing Architecture for Code Compilation

Role of Multiblocks in Control Flow Prediction using Parallel Register Sharing Architecture

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