Exploiting forwarding to improve data bandwidth of instruction-set extensions

Abstract

Application-specific instruction-set extensions (custom instructions) help embedded processors achieve higher performance. Most custom instructions offering significant performance benefit require multiple input operands. Unfortunately, RISC-style embedded processors are designed to support at most two input operands per instruction. This data bandwidth problem is due to the limited number of read ports in the register file per instruction as well as the fixed-length instruction encoding. We propose to overcome this restriction by exploiting the data forwarding feature present in processor pipelines. With minimal modifications to the pipeline and the instruction encoding along with cooperation from the compiler, we can supply up to two additional input operands per custom instruction. Experimental results indicate that our approach achieves 87-100% of the ideal performance limit for standard benchmark programs. Additionally, our scheme saves 25% energy on an average by avoiding unnecessary accesses to the register file.

An energy-efficient method of supporting flexible special instructions in an embedded processor with compact ISA

“…Utilizing the bypass network has been proven an efficient way to increase operand bandwidth and reduce register file energy in different types of architectures [She et al 2012b;Balfour et al 2007Balfour et al , 2009Park et al 2006]. Jayaseelan et al proposed explicit forwarding to reduce register file port pressure and operand encoding cost for application-specific ISE in a RISC-like datapath, which resembles the idea of explicit bypass in this work [Jayaseelan et al 2006]. However, the power model used in Jayaseelan et al [2006] only considers the consumption of the register file.…”

“…There are also studies trying to integrate ISE in general-purpose architectures [Clark et al 2004[Clark et al , 2005Jayaseelan et al 2006]. Most of these focus on improving the performance.…”

“…Jayaseelan et al proposed explicit forwarding to reduce register file port pressure and operand encoding cost for application-specific ISE in a RISC-like datapath, which resembles the idea of explicit bypass in this work [Jayaseelan et al 2006]. However, the power model used in Jayaseelan et al [2006] only considers the consumption of the register file. The overall energy efficiency of the proposed architecture is not clear.…”

“…But the fine-grained control over the datapath also introduces overhead in code density, resulting in increased fetching and decoding energy. In Jayaseelan et al [2006], Integer Linear Programming (ILP) is used to perform bypass-aware scheduling in a processor with application-specific ISE. The proposed algorithm inserts register copying instructions in order to meet the constraints of the special instructions.…”

On Data Forwarding in Deeply Pipelined Soft Processors

“…This can increase performance by reducing the number of NOP instructions required between dependent instructions. It has been explored in the context of general soft processor design, VLIW embedded processors [17], as well as instruction set extensions in soft processors [12]. In each case, the principle is to allow the result of an ALU computation to be accessed sooner than would be possible in the case where write back must occur prior to execution of a subsequent dependent instruction.…”