A Modern Parallel Register Sharing Architecture for Code Compilation

Abstract

The design of many-core-on-a-chip has allowed renewed an intense interest in parallel computing. On implementation part, it has been seen that most of applications are not able to use enough parallelism in parallel register sharing architecture. The exploitation of potential performance of superscalar processors has shown that processor is fed with sufficient instruction bandwidth. The fetcher and the Instruction Stream Buffer (ISB) are the key elements to achieve this target. Beyond the basic blocks, the instruction stream is not supported by currents ISBs. The split line instruction problem depreciates this situation for x86 processors. With the implementation of Line Weighted Branch Target Buffer (LWBTB), the advance branch information and reassembling of cache lines can be predicted by the ISB. The ISB can fetch some more valid instructions in a cycle through reassembling of original line containing instructions for next basic block. If the cache line size is more than 64 bytes, then there exist good chances to have two basic blocks in the recognized instruction line.The code generation for parallel register share architecture involves some issues that are not present in sequential code compilation and is inherently complex. To resolve such issues, a consistency contract between the code and the machine can be defined and a compiler is required to preserve the contract during the transformation of code. In this paper, we present a correctness framework to ensure the protection of the contract and then we use code optimization for verification under parallel code.

A novel heuristic for selection of hyperblock in If-conversion

“…[2] presents role of multiblocks in control flow prediction (CFP) in parallel register sharing architecture to achieve high degree of ILP. The parallel register sharing architecture for code compilation is presented in [1]. [3] introduces control flow prediction (CFP) in parallel register sharing architecture.…”

Simulation of Branch Prediction Optimization in ParallelRegister Sharing Architecture

“…A strategy has been represented in [11] to reduce the number of off chip references due to shared data. In contrast to [3], an aggressive register reclamation mechanism targeted to micro-architecture is presented in [12] by Salvador Petit Martı et. al.…”

“…This short of knowledge creates several problems like (1) branch prediction and (2) its identity. It means the branch must be encountered by parallel register sharing architecture [3].…”

Role of Multiblocks in Control Flow Prediction using Parallel Register Sharing Architecture

“…The ISB (Instruction Stream Buffer) architecture and the ISB structure are presented in [12] for control flow prediction. The information presented in CFG for a program can be exploited by ISB architecture that presents parallelization of shared register after inspection of control flow graph of a program, it is possible to infer that some of the basic blocks may be executed regardless previous branch outcome.…”

“…This short of knowledge creates several problems like (1) branch prediction and (2) its identity. It means the branch must be encountered by parallel register sharing architecture [12]. Due to normal branch prediction, a prediction can be made while the fetch unit fetches the branch instruction for their execution.…”