Architectural Support for Mitigating Row Hammering in DRAM Memories

Abstract

DRAM scaling has been the prime driver of increasing capacity of main memory systems. Unfortunately, lower technology nodes worsen the cell reliability as it increases the coupling between adjacent DRAM cells, thereby exacerbating different failure modes. This paper investigates the reliability problem due to Row Hammering, whereby frequent activations of a given row can cause data loss for its neighboring rows. As DRAM scales to lower technology nodes, the threshold for the number of row activations that causes data loss for the neighboring rows reduces, making Row Hammering a challenging problem for future DRAM chips. To overcome Row Hammering, we propose two architectural solutions: First, Counter-Based Row Activation (CRA), which uses a counter with each row to count the number of row activations. If the count exceeds the row hammering threshold, a dummy activation is sent to neighboring rows proactively to refresh the data. Second, Probabilistic Row Activation (PRA), which obviates storage overhead of tracking and simply allows the memory controller to proactively issue dummy activations to neighboring rows with a small probability for all memory access. Our evaluations show that these solutions are effective at mitigating Row hammering while causing negligible performance loss (< 1 percent).

RowHammer: A Retrospective

“…Thus, stronger ECC is very likely required to correct RowHammer errors, which comes at the cost of additional energy, performance, cost, and DRAM capacity overheads. 4 Alternatively, the sixth solution described above, i.e., accurately identifying a row as a hammered row requires keeping track of access counters for a large number of rows in the memory controller [120], potentially leading to very large hardware area and power consumption, and performance, overheads.…”

Under Quantum Computer Attack: Is Rainbow a Replacement of RSA and Elliptic Curves on Hardware?

“…The underlying principle of side channel attack is that side channel information such as power consumption, electromagnetic leaks, timing information, or even sound can provide extra sources of information about secrets in cryptographic systems, for example, cryptographic keys, partial state information, full or partial plain texts, which can be exploited to break the cryptographic systems. General classes of side channel attack include timing analysis [31], power analysis [32], electromagnetic analysis [33], fault analysis [34], acoustic cryptanalysis [35], data remanence analysis [36], and row hammer analysis attacks [37].…”

Mitigating Wordline Crosstalk Using Adaptive Trees of Counters

“…There are two main hardware approaches to mitigate wordline crosstalk in DRAM. The first relies on a random number generator [24,25] in the memory controller to probabilistically refresh accessed rows [26]. Although the idea behind this approach is simple, it results in an early refresh of rows that can be potentially affected by crosstalk [15], as well as unnecessary row refreshing in the absence of hot rows.…”

“…However, having one counter per row induces a significant area and power overhead to the memory system. To prevent this high cost, row activation counters can be stored in a reserved area of the main memory and a dedicated on-chip countercache can be used to minimize the performance penalty of retrieving counter values from main memory [26].…”

“…A hardware approach to alleviate wordline crosstalk is for each DRAM access to refresh the victim rows adjacent to the accessed row based on a probability function [26]. In this probabilistic approach, called PRA (Probabilistic Row Activation), the memory controller uses a Pseudo-Random Number Generator with a given probability (α) to determine when the memory controller should issue a refresh signal to refresh the two rows adjacent to the accessed row.…”