Architectural Semantics for Practical Transactional Memory

McDonald, Austen; Chung, JaeWoong; Carlstrom, Brian D.; Minh, Chi Cao; Chafi, Hassan; Kozyrakis, Christos; Olukotun, Kunle

doi:10.1109/isca.2006.9

Cited by 112 publications

(100 citation statements)

References 26 publications

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“…For example, many flat and closed-nested transactions can be recorded as a single episode corresponding to the outermost transaction, as done for Atlas [14]. Future work can examine how Rerun interacts with transactional memory subtleties, such as open-nested transactions and compensating actions [22,24].…”

Section: Extensibilitymentioning

confidence: 99%

Rerun: Exploiting Episodes for Lightweight Memory Race Recording

Hower

Hill

2008

2008 International Symposium on Computer Architecture

135

136

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Section: Extensibilitymentioning

confidence: 99%

Rerun: Exploiting Episodes for Lightweight Memory Race Recording

Hower

Hill

2008

2008 International Symposium on Computer Architecture

135

136

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“…To reduce the cost for re-execution, some techniques for optimizing rollbacks have been proposed [10]- [12]. Besides, many thread scheduling techniques for reducing conflicts by controlling transactional sequences have been also proposed [13]- [15].…”

Section: Related Workmentioning

confidence: 99%

A Waiting Mechanism with Conflict Prediction on Hardware Transactional Memory

Mashita

Tabuchi

Yamada

et al. 2016

IEICE Trans. Inf. & Syst.

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SUMMARYLock-based thread synchronization techniques have been commonly used in parallel programming on multi-core processors. However, lock can cause deadlocks and poor scalabilites, and Transactional Memory (TM) has been proposed and studied for lock-free synchronization. On TMs, transactions are executed speculatively in parallel as long as they do not encounter any conflicts on shared variables. On general HTMs: hardware implementations of TM, transactions which have conflicted once each other will conflict repeatedly if they will be executed again in parallel, and the performance of HTM will decline. To address this problem, in this paper, we propose a conflict prediction to avoid conflicts before executing transactions, considering historical data of conflicts. The result of the experiment shows that the execution time of HTM is reduced 59.2% at a maximum, and 16.8% on average with 16 threads.

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“…The rest of the registers are selectively checkpointed by software in the interest of saving hardware cost. Nested speculative regions are supported through flat nesting -parent speculative regions subsume child speculative regions [14].…”

Section: Asf Isamentioning

confidence: 99%

ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory

Chung

Yen

Diestelhorst

et al. 2010

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Advanced Synchronization Facility (ASF) is an AMD64 hardware extension for lock-free data structures and transactional memory. It provides a speculative region that atomically executes speculative accesses in the region. Five new instructions are added to demarcate the region, use speculative accesses selectively, and control the speculative hardware context. Programmers can use speculative regions to build flexible multi-word atomic primitives with no additional software support by relying on the minimum guarantee of available ASF hardware resources for lock-free programming. Transactional programs with high-level TM language constructs can either be compiled directly to the ASF code or be linked to software TM systems that use ASF to accelerate transactional execution. In this paper we develop an out-of-order hardware design to implement ASF on a future AMD processor and evaluate it with an in-house simulator. The experimental results show that the combined use of the L1 cache and the LS unit is very helpful for the performance robustness of ASF-based lockfree data structures, and that the selective use of speculative accesses enables transactional programs to scale with limited ASF hardware resources.

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Architectural Semantics for Practical Transactional Memory

Cited by 112 publications

References 26 publications

Rerun: Exploiting Episodes for Lightweight Memory Race Recording

Rerun: Exploiting Episodes for Lightweight Memory Race Recording

A Waiting Mechanism with Conflict Prediction on Hardware Transactional Memory

ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory

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