ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory

Abstract

Abstract-Advanced Synchronization Facility (ASF) is an AMD64 hardware extension for lock-free data structures and transactional memory. It provides a speculative region that atomically executes speculative accesses in the region. Five new instructions are added to demarcate the region, use speculative accesses selectively, and control the speculative hardware context. Programmers can use speculative regions to build flexible multi-word atomic primitives with no additional software support by relying on the minimum guarantee of available ASF hardware resources for lock-free programming. Transactional programs with high-level TM language constructs can either be compiled directly to the ASF code or be linked to software TM systems that use ASF to accelerate transactional execution. In this paper we develop an out-of-order hardware design to implement ASF on a future AMD processor and evaluate it with an in-house simulator. The experimental results show that the combined use of the L1 cache and the LS unit is very helpful for the performance robustness of ASF-based lockfree data structures, and that the selective use of speculative accesses enables transactional programs to scale with limited ASF hardware resources.

Study of hardware transactional memory characteristics and serialization policies on Haswell

“…Two transactions conflict when they access the same address and one of them writes to it. A Hardware TM (HTM) system uses dedicated hardware to accelerate transactional execution [7][8][9] . The HTM system starts a transaction by executing a register checkpoint with shadow register files.…”

Software Support and Evaluation of Hardware Transactional Memory on Blue Gene/Q

“…For the HTM by Azul, there is little public disclosure on the implementation and no performance study of the TM support [8]. The specification of a hardware extension for TM in the AMD64 architecture has yet to be released in hardware [7]. Recently IBM [4], [13], [16] and Intel [15] disclosed that they are releasing implementations of HTM.…”

“…Good scaling via effective HTM: genome, vacation, scalparc, and utilitymine exhibit a good scalability and a low serialization ratio. 7 Both genome and vacation are heavily synchronized leading the lock implementation to completely serialize and the TM implementation scales much better. Performance boosts beyond 16 threads come from SMT threads multiplexing on the processor pipeline and from hiding in-order processor stalls.…”

Opportunities and pitfalls of multi-core scaling using hardware transaction memory

“…Examples include Sun's Rock processor [5], AMD advanced synchronization family [7], Intel transitional synchronization extensions (TSX) [1] and IBM Blue Gene/Q [17]. Among these proposals and implementations, the recent release of Haswell processor with Intel TSX marks the wide availability of HTM on the mass market.…”