Architecting reliable multi-core network-on-chip for small scale processing technology

Abstract

The trend towards multi-Imany-core design has made network on-chip (NoC) a crucial component of future microprocessors. With CMOS processing technologies continuously scaling down to the nanometer regime, effects such as process variation (PV) and negative bias temperature instability (NBT!) significantly decrease hardware reliability and lifetime. Therefore, it is imperative for multi-core architects to consider and mitigate these effects in NoCs implemented using small-scale processing technology. This paper reports on a first step to optimize NoC architecture reliability in light of both PV and NBT! effects. We propose novel techniques that can hierarchically alleviate PV and NBT! effects on NoC while leveraging their benign interaction. Our low-level design improves PV and NBT! efficiency of key components (e.g. virtual channel allocation logics, virtual channels) of critical paths of the pipelined router microarchitecture. Our high-level mechanisms leverage NBT! degradation and PV information from multiple routers to intelligently route packets, delivering optimized performance power-reliability across the NoC substrate. Experimental results show that our intra-router level techniques (i.e. VA_M1 and VC _ M2) reduce guardband by 47% while improving network throughput by 24%. Our inter-router optimization scheme (i.e. 1R_M3) results in 50% guardband reduction and 19% network latency improvement.

Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks

“…Vicis is a redundancy-based microarchitectural technique that provides system-level fault-tolerance for routers in an NoC when dealing with a few hard faults caused by gradual wearout [12]. Fu et al consider both process variations and negative bias temperature instability (NBTI) effects on NoC router pipelines [13]. Li et al studied the design of an NoC under process variations and realized that a high degree of process variations can force major design modifications to the underlying network architecture [29].…”

“…This results in energy-inefficient designs. On-chip networks can already consume a substantial fraction of the on-chip power -potentially up to 30-40%, according to the literature [4,6,8,13,17,29]. Conservative future network designs, needed to tolerate parameter variations, may be unable to reduce the value of this fraction much.…”

A sensor-less NBTI mitigation methodology for NoC architectures

“…Xin Fu et al present a comprehensive approach to mitigate NBTI degradation considering NoC architectures [14]. This work presents several approaches to effectively manage NBTI impact, focusing on different micro-architectural components, namely buffers and arbiters.…”

“…This work presents several approaches to effectively manage NBTI impact, focusing on different micro-architectural components, namely buffers and arbiters. However, [14] does not exploit the information on actual NoC traffic between each router pair, thus the solution looses the possibility to aggressively reduce NBTI degradation as well as the exploitation of NBTI/performance trade-off.…”

“…Process variation is a combination of random effects and systematic effects [24], and can impact both die-to-die and within-die parameters. In this work we are mainly interested in within-die process variation, and assume for simplicity the impact of die-to-die variation to be constant in the same chip [14]. Process variability manifests itself as a divergence of sensible design parameters (e.g., initial threshold voltage V th ) from their nominal values.…”