Application of Machine Learning in Hardware Trojan Detection

Kundu, Shamik; Meng, Xingyu; Basu, Kanad

doi:10.1109/isqed51717.2021.9424362

Cited by 18 publications

(9 citation statements)

References 32 publications

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“…from soft adware which only seek to show ads to the users. At the same time, there also is a vast literature about the application of ML models to detect HTHs, as it is demonstrated by a number of recently published surveys on the topic [36][37][38]. All these works agree in highlighting the following research directions that have not been taken into account yet:…”

Section: Introduction and Related Workmentioning

confidence: 94%

Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer

Palumbo

Cassano

Luzzi

et al. 2022

Journal of Systems Architecture

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Section: Introduction and Related Workmentioning

confidence: 94%

Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer

Palumbo

Cassano

Luzzi

et al. 2022

Journal of Systems Architecture

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“…Despite the substantial advancements in machine learning (ML)-based trojan detection techniques aiming to reduce reliance on a golden model, we opt for utilizing a reference model for trojan detection. ML-based methods are still in their early stages [25,32] and encounter difficulties in automating and ensuring accuracy, which poses risks of misclassifying trojans and allowing them to evade detection. Nonetheless, our approach remains adaptable to situations where a golden model is unavailable, relying on test generation driven by coverage of infrequent triggers to systematically uncover potential hidden malicious circuitry within the design.…”

Section: Motivationmentioning

confidence: 99%

GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs

Debnath

Chowdhury

Saha

et al. 2022

2022 IEEE International Test Conference (ITC)

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High-Level Synthesis (HLS) has transformed the development of complex Hardware IPs (HWIP) by offering abstraction and configurability through languages like SystemC/C++, particularly for Field Programmable Gate Array (FPGA) accelerators in high-performance and cloud computing contexts. These IPs can be synthesized for different FPGA boards in cloud, offering compact area requirements and enhanced flexibility. HLS enables designs to execute directly on ARM processors within modern FPGAs without the need for Register Transfer Level (RTL) synthesis, thereby conserving FPGA resources. While HLS offers flexibility and efficiency, it also introduces potential vulnerabilities such as the presence of hidden circuitry, including the possibility of hosting hardware trojans within designs.In cloud environments, these vulnerabilities pose significant security concerns such as leakage of sensitive data, IP functionality disruption and hardware damage, necessitating the development of robust testing frameworks. This research presents an advanced testing approach for HLS-developed cloud IPs, specifically targeting hidden malicious functionalities that may exist in rare conditions within the design. The proposed method leverages selective instrumentation, combining greybox fuzzing and concolic execution techniques to enhance test generation capabilities. Evaluation conducted on various HLS benchmarks, possessing characteristics of FPGA-based cloud IPs with embedded cloud related threats, demonstrates the effectiveness of our framework in detecting trojans and rare scenarios, showcasing improvements in coverage, time efficiency, memory usage, and testing costs compared to existing methods.

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“…Trojans can be inserted locally or distributed throughout the network. The payload and the trigger part of the Trojan can be digital or analog, as malicious modification can occur when the temperature of the chip changes [9].…”

Section: Introductionmentioning

confidence: 99%

Hardware Trojan Mitigation Technique in Network-on-Chip (NoC)

et al. 2023

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Due to globalization in the semiconductor industry, malevolent modifications made in the hardware circuitry, known as hardware Trojans (HTs), have rendered the security of the chip very critical. Over the years, many methods have been proposed to detect and mitigate these HTs in general integrated circuits. However, insufficient effort has been made for hardware Trojans (HTs) in the network-on-chip. In this study, we implement a countermeasure to congeal the network-on-chip hardware design in order to prevent changes from being made to the network-on-chip design. We propose a collaborative method which uses flit integrity and dynamic flit permutation to eliminate the hardware Trojan inserted into the router of the NoC by a disloyal employee or a third-party vendor corporation. The proposed method increases the number of received packets by up to 10% more compared to existing techniques, which contain HTs in the destination address of the flit. Compared to the runtime HT mitigation method, the proposed scheme also decreases the average latency for the hardware Trojan inserted in the flit’s header, tail, and destination field up to 14.7%, 8%, and 3%, respectively.

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Application of Machine Learning in Hardware Trojan Detection

Cited by 18 publications

References 32 publications

Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer

Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer

GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs

Hardware Trojan Mitigation Technique in Network-on-Chip (NoC)

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