Achieving efficient spatial modulation of phonon transmission is an essential step on the path to phononic circuits using "phonon currents". With their intrinsic and reconfigurable interfaces, domain walls (DWs), ferroelectrics are alluring candidates to be harnessed as dynamic heat modulators. This paper reports the thermal conductivity of single-crystal PbTiO 3 thin films over a wide variety of epitaxial-strain-engineered ferroelectric domain configurations. The phonon transport is proved to be strongly affected by the density and type of DWs, achieving a 61% reduction of the room-temperature thermal conductivity compared to the single-domain scenario. The thermal resistance across the ferroelectric DWs is obtained, revealing a very high value (≈5.0 × 10 −9 K m 2 W −1 ), comparable to grain boundaries in oxides, explaining the strong modulation of the thermal conductivity in PbTiO 3 . This low thermal conductance of the DWs is ascribed to the structural mismatch and polarization gradient found between the different types of domains in the PbTiO 3 films, resulting in a structural inhomogeneity that extends several unit cells around the DWs. These findings demonstrate the potential of ferroelectric DWs as efficient regulators of heat flow in one single material, overcoming the complexity of multilayers systems and the uncontrolled distribution of grain boundaries, paving the way for applications in phononics.

In nanometer technology regime, design components mandate their reuse to meet the complex design challenges and hence comprise Intellectual Property (IP). Unauthorized reuse raises major security issues. IP mark(s) is embedded into a design for establishing the veracity of a legal IP owner/buyer. However, methods for trustworthy public verification of IP marks are not secure. For field-programmable gate-array (FPGA) designs, marks become prone to tampering, and even being overridden by an attacker's signature after public verification. In order to ensure trustworthy yet leakage-proof public verification based on the marks hidden in a FPGA design, we propose a zero-knowledge protocol Verify_ZKP. It is an interactive two-person game between the prover and the verifier. This protocol is fast, incurs no additional design overhead, and needs no centralized signature database. We establish that Verify_ZKP satisfies zero-knowledge property, and introduce statistical metrics to measure its robustness. We have simulated our protocol for IWLS'05 FPGA benchmarks. Experimental results on robustness and overhead are very encouraging.Index Terms-Design-for-security, VLSI field-programmable gate-array (FPGA) design, watermark verification, zero-knowledge protocol.

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Bulk SrTiO 3 is a quantum paraelectric in which an antiferrodistortive distortion below ≈105 K and quantum fluctuations at low temperature preclude the stabilization of a long-range ferroelectric state. However, biaxial mechanical stress, impurity doping, and Sr nonstoichiometry, among other mechanisms, are able to stabilize a ferroelectric or relaxor ferroelectric state at room temperature, which develops into a longer-range ferroelectric state below 250 K. In this paper, we show that epitaxial SrTiO 3 thin films grown under tensile strain on DyScO 3 exhibit a large reduction of thermal conductivity, of ≈60% at room temperature, with respect to identical strain-free or compressed films. The thermal conductivity shows a further reduction below 250 K, a temperature concurrent with the peak in the dielectric constant [J. H. Haeni et al., Nature (London) 430, 758 (2004)]. These results suggest that strain gradients in the relaxor and ferroelectric phase of SrTiO 3 are very effective phonon scatterers, limiting the thermal transport in this material.

Increased design complexity, shrinking design cycle, and low cost—this three-dimensional demand mandates advent of system-on-chip (SoC) methodology in semiconductor industry. The key concept of SoC is reuse of the intellectual property (IP) cores. Reuse of IPs on SoC increases the risk of misappropriation of IPs due to introduction of several new attacks and involvement of various parties as adversaries. Existing literature has huge number of proposals for IP protection (IPP) techniques to be incorporated in the IP design flow as well as in the SoC design methodology. However, these are quite scattered, limited in possibilities in multithreat environment, and sometimes mutually conflicting. Existing works need critical survey, proper categorization, and summarization to focus on the inherent tradeoff, existing security holes, and new research directions. This paper discusses the IP-based SoC design flow to highlight the exact locations and the nature of infringements in the flow, identifies the adversaries, categorizes these infringements, and applies strategic analysis on the effectiveness of the existing IPP techniques for these categories of infringements. It also clearly highlights recent challenges and new opportunities in this emerging field of research.

As first recognized in 2010, epitaxial graphene on SiC(0001) provides a platform for quantized Hall resistance (QHR) metrology unmatched by other two-dimensional structures and materials. Here we report graphene parallel QHR arrays, with metrologically precise quantization near 1000 Ω. These arrays have tunable carrier densities, due to uniform epitaxial growth and chemical functionalization, allowing quantization at the robust ν = 2 filling factor in array devices at relative precision better than 10 −8 . Broad tunability of the carrier density also enables investigation of the ν = 6 plateau. Optimized networks of QHR devices described in this work suppress Ohmic contact resistance error using branched contacts and avoid crossover leakage with interconnections that are superconducting for quantizing magnetic fields up to 13.5 T. Our work enables more direct scaling of resistance for quantized values in arrays of arbitrary network geometry.