Application of fast wafer-level reliability PBTI tests for screening of High-k / Metal Gate process splits

As-grown-Generation Model for Positive Bias Temperature Instability

“…It is worth of noting that the extracted GD has a Vgov-independent time exponent of 0.32. This is larger than that extracted from the total ΔVth in Fig.1a and most of the values reported by early works [1][2][3][4][5][6][7][8] in Fig.1d. It is also larger than the ~0.2 reported for NBTI [21].…”

“…However, the classic power law model extracted from these data failed to predict the PBTI even just 0.1V below the lowest Vgst used for model parameter extraction, as shown in Fig.1c. When fitting the measured ΔVth, the uncertainties for the time exponent reported by early works in Fig.1d [1][2][3][4][5][6][7][8] do not warrant prediction. There is a need for a test-proven method to characterize and model PBTI induced degradation, enabling reliable prediction.…”

“…geing has become a critical concern for CMOS technologies as scaling is reaching nano-scale regime [1][2][3][4][5][6][7][8]. Thorough examination and certification of reliable operation throughout the entire application lifetime is required during design.…”

“…Extensive efforts have been made in investigating the Negative Bias Temperature Instability (NBTI) for pFETs. The recent use of the multi-layer gate material, however, has led to considerable Positive Bias Temperature Instability (PBTI) for nFETs [1][2][3][4][5][6][7][8]. From the application perspective, it has been reported that PBTI can be the dominating reliability issue for Field-Programmable Gate Arrays (FPGAs) [10] and Ring Oscillators (RO) [11].…”

“…Despite industry-wide characterization of various aspects of PBTI phenomena and general consensus regarding its empirical features [1][2][3][4][5][6][7][8][9][10][11], the detailed mechanism of the degradation is not fully understood. Charging of pre-existing traps and/or generating new traps in the dielectric are considered to be the root of PBTI [12].…”