Application design trajectory towards reusable coprocessors MPEG case study

Rutten, Martijn J.; Gangwal, Om Prakash; Eijndhoven, J. van; Jaspers, E.G.T.; Pol, Evert-Jan D.

doi:10.1109/estmed.2004.1359699

Cited by 4 publications

(3 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Other research works aimed to an increased flexibility [7] and/or to speed up different applications [22]. Milakovic et al [7] presented the implementation of a co-processor capable of switching among different datapaths.…”

Section: B Co-processing Units: Automatic Generationmentioning

confidence: 99%

“…The MDC approach is different: shared resources are (de)multiplexed over a unique datapath and the co-processing unit can be automatically derived using the design flow we are proposing. Rutten et al [22] also considered a multi-application case: common functions (computational kernels) are identified exploiting a dataflow formalism. Kernels are then mapped into different non-reconfigurable hardware accelerators, alternatively invoked when required by the current execution.…”

Section: B Co-processing Units: Automatic Generationmentioning

confidence: 99%

“…Finally, the complete design flow allows defining automatically any type of platform. If data parallelism needs to be managed, as in [22], more than one reconfigurable (even heterogeneous, dealing with different starting high-level descriptions) co-processor can be instantiated. The automation of the generation process, from high-level to RTL, makes it possible to couple this flow with dataflowbased partitioning algorithms.…”

Section: Co-processor Generatormentioning

confidence: 99%

See 2 more Smart Citations

Automatic generation of dataflow-based reconfigurable co-processing units

Palumbo

2014

Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing

View full text Add to dashboard Cite

Hardware accelerators are widely adopted to speed up computationally onerous applications. However their design is not trivial, especially if multiple applications/kernels need to be served. To this aim the Multi-Dataflow Composer (MDC) tool can be adopted to generate the internal computing core of flexible and reconfigurable hardware accelerators. Nevertheless, MDC is not able, as it is, to deploy ready to use accelerators. To address this lack, we conceived a fully automated design flow for coarse-grained reconfigurable and memory-mapped hardware accelerators, which required: a) the definition of a generic co-processing template, the Template Interface Layer; b) the extension of the MDC tool to characterize such a template and deploy the accelerators. This methodology represents, within MPEG Reconfigurable Video Coding studies, the first framework for the automatic generation of reconfigurable hardware accelerators and, as it will be discussed, it may be beneficial also in other contexts of execution with fairly limited adjustments. Results validated the proposed approach in a real use case scenario, comparing the automatically generated co-processor with a previous custom one.

show abstract

Section: B Co-processing Units: Automatic Generationmentioning

confidence: 99%

Section: B Co-processing Units: Automatic Generationmentioning

confidence: 99%

Section: Co-processor Generatormentioning

confidence: 99%

See 1 more Smart Citation

Automatic generation of dataflow-based reconfigurable co-processing units

Palumbo

2014

Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing

View full text Add to dashboard Cite

show abstract

Automated Design Flow for Multi-Functional Dataflow-Based Platforms

Meloni

Raffo

et al. 2015

J Sign Process Syst

View full text Add to dashboard Cite

The implementation of processing platforms supporting multiple applications by runtime reconfigurations on dedicated hardware modules requires the solution of different problems. These problems are notably not-trivial since both platform and application complexities increase year after year. As a consequence, the design process is both time and resource demanding. System configuration along with resources management and mapping remain one of the most challenging problem, particularly when runtime adaptation is required. In this direction, the ISO/IEC SC29WG11 committee (MPEG) has developed the so called MPEG-RVC standards ISO/IEC 23001-4 and 23002-4. This standard provides specifications of video codecs in the form of dataflow programs. In this paper, an integrated design flow to derive optimized multi-functional platforms directly from disjoined high-level specifications is presented. To the authors’ best of knowledge, such an optimization, synthesis and mapping methodology for coarse-grained reconfigurable systems design does not exist within the MPEG-RVC framework. The design flow presented in this paper leverages on an integrated set of independently designed tools, all supporting the RVC standard. Results assessment has been carried out on three different scenarios: an MPEG-RVC decoder, a standard baseline MPEG-RVC JPEG codec and a generalized reconfigurable multi-quality JPEG encoder. For all these scenarios, the proposed design flow has been targeted for a Xilinx Virtex 5 FPGA. Results show how this approach is capable of yielding a reconfigurable design that preserves the original performance of the stand alone non-reconfigurable platform providing, at the same time, considerable area savings featuring a larger set of functionalities. Moreover, platforms programmability, on the basis of the required functionality ID, is automatically handled at runtime without any designer effort

show abstract